📄 prev_cmp_clock.qmsg
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{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.fit.smsg " "Info: Generated suppressed messages file F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "165 " "Info: Allocated 165 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 20 14:08:22 2009 " "Info: Processing ended: Tue Jan 20 14:08:22 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 20 14:08:31 2009 " "Info: Processing started: Tue Jan 20 14:08:31 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off clock -c clock " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off clock -c clock" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" { } { } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "125 " "Info: Allocated 125 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Jan 20 14:08:35 2009 " "Info: Processing ended: Tue Jan 20 14:08:35 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 20 14:08:37 2009 " "Info: Processing started: Tue Jan 20 14:08:37 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off clock -c clock" { } { } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "segdat_reg\[0\] " "Warning: Node \"segdat_reg\[0\]\" is a latch" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segdat_reg\[1\] " "Warning: Node \"segdat_reg\[1\]\" is a latch" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segdat_reg\[2\] " "Warning: Node \"segdat_reg\[2\]\" is a latch" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segdat_reg\[3\] " "Warning: Node \"segdat_reg\[3\]\" is a latch" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segdat_reg\[4\] " "Warning: Node \"segdat_reg\[4\]\" is a latch" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segdat_reg\[5\] " "Warning: Node \"segdat_reg\[5\]\" is a latch" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segdat_reg\[6\] " "Warning: Node \"segdat_reg\[6\]\" is a latch" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } } } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} } { } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 2 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "22 " "Warning: Found 22 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Mux0~29 " "Info: Detected gated clock \"Mux0~29\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux0~29" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux0~28 " "Info: Detected gated clock \"Mux0~28\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux0~28" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux1~28 " "Info: Detected gated clock \"Mux1~28\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux1~28" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux1~27 " "Info: Detected gated clock \"Mux1~27\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux1~27" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux2~18 " "Info: Detected gated clock \"Mux2~18\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux2~18" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "min\[6\] " "Info: Detected ripple clock \"min\[6\]\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "min\[6\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "min\[7\] " "Info: Detected ripple clock \"min\[7\]\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "min\[7\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "min\[5\] " "Info: Detected ripple clock \"min\[5\]\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "min\[5\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux2~17 " "Info: Detected gated clock \"Mux2~17\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux2~17" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "min\[3\] " "Info: Detected ripple clock \"min\[3\]\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "min\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "min\[2\] " "Info: Detected ripple clock \"min\[2\]\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "min\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "min\[1\] " "Info: Detected ripple clock \"min\[1\]\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "min\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sec\[6\] " "Info: Detected ripple clock \"sec\[6\]\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 62 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sec\[6\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sec\[7\] " "Info: Detected ripple clock \"sec\[7\]\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 62 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sec\[7\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sec\[5\] " "Info: Detected ripple clock \"sec\[5\]\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 62 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sec\[5\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sec\[3\] " "Info: Detected ripple clock \"sec\[3\]\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 62 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sec\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sec\[1\] " "Info: Detected ripple clock \"sec\[1\]\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 62 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sec\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sec\[2\] " "Info: Detected ripple clock \"sec\[2\]\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 62 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sec\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "second " "Info: Detected ripple clock \"second\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 12 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "second" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cn " "Info: Detected ripple clock \"cn\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 13 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "cn" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count\[10\] " "Info: Detected ripple clock \"count\[10\]\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count\[10\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count\[11\] " "Info: Detected ripple clock \"count\[11\]\" as buffer" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count\[11\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register min\[3\] register segdat_reg\[5\] 68.57 MHz 14.584 ns Internal " "Info: Clock \"clk\" has Internal fmax of 68.57 MHz between source register \"min\[3\]\" and destination register \"segdat_reg\[5\]\" (period= 14.584 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.005 ns + Longest register register " "Info: + Longest register to register delay is 5.005 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns min\[3\] 1 REG LC_X4_Y4_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N7; Fanout = 4; REG Node = 'min\[3\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { min[3] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.956 ns) + CELL(0.511 ns) 1.467 ns Mux0~28 2 COMB LC_X4_Y4_N1 1 " "Info: 2: + IC(0.956 ns) + CELL(0.511 ns) = 1.467 ns; Loc. = LC_X4_Y4_N1; Fanout = 1; COMB Node = 'Mux0~28'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.467 ns" { min[3] Mux0~28 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.727 ns) + CELL(0.200 ns) 2.394 ns Mux0~29 3 COMB LC_X4_Y4_N0 5 " "Info: 3: + IC(0.727 ns) + CELL(0.200 ns) = 2.394 ns; Loc. = LC_X4_Y4_N0; Fanout = 5; COMB Node = 'Mux0~29'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.927 ns" { Mux0~28 Mux0~29 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.906 ns) + CELL(0.200 ns) 4.500 ns Mux9~29 4 COMB LC_X2_Y4_N3 1 " "Info: 4: + IC(1.906 ns) + CELL(0.200 ns) = 4.500 ns; Loc. = LC_X2_Y4_N3; Fanout = 1; COMB Node = 'Mux9~29'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.106 ns" { Mux0~29 Mux9~29 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.005 ns segdat_reg\[5\] 5 REG LC_X2_Y4_N4 1 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 5.005 ns; Loc. = LC_X2_Y4_N4; Fanout = 1; REG Node = 'segdat_reg\[5\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { Mux9~29 segdat_reg[5] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.111 ns ( 22.20 % ) " "Info: Total cell delay = 1.111 ns ( 22.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.894 ns ( 77.80 % ) " "Info: Total interconnect delay = 3.894 ns ( 77.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.005 ns" { min[3] Mux0~28 Mux0~29 Mux9~29 segdat_reg[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.005 ns" { min[3] {} Mux0~28 {} Mux0~29 {} Mux9~29 {} segdat_reg[5] {} } { 0.000ns 0.956ns 0.727ns 1.906ns 0.305ns } { 0.000ns 0.511ns 0.200ns 0.200ns 0.200ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.204 ns - Smallest " "Info: - Smallest clock skew is 0.204 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.209 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 12.209 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 24 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 24; CLK Node = 'clk'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns count\[10\] 2 REG LC_X4_Y4_N5 12 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X4_Y4_N5; Fanout = 12; REG Node = 'count\[10\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk count[10] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.595 ns) 4.319 ns Mux2~17 3 COMB LC_X4_Y4_N5 1 " "Info: 3: + IC(0.000 ns) + CELL(0.595 ns) = 4.319 ns; Loc. = LC_X4_Y4_N5; Fanout = 1; COMB Node = 'Mux2~17'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.595 ns" { count[10] Mux2~17 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.824 ns Mux2~18 4 COMB LC_X4_Y4_N6 8 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 4.824 ns; Loc. = LC_X4_Y4_N6; Fanout = 8; COMB Node = 'Mux2~18'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { Mux2~17 Mux2~18 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.744 ns) + CELL(0.740 ns) 7.308 ns Mux11~29 5 COMB LC_X2_Y4_N6 7 " "Info: 5: + IC(1.744 ns) + CELL(0.740 ns) = 7.308 ns; Loc. = LC_X2_Y4_N6; Fanout = 7; COMB Node = 'Mux11~29'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { Mux2~18 Mux11~29 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.390 ns) + CELL(0.511 ns) 12.209 ns segdat_reg\[5\] 6 REG LC_X2_Y4_N4 1 " "Info: 6: + IC(4.390 ns) + CELL(0.511 ns) = 12.209 ns; Loc. = LC_X2_Y4_N4; Fanout = 1; REG Node = 'segdat_reg\[5\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.901 ns" { Mux11~29 segdat_reg[5] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.503 ns ( 36.88 % ) " "Info: Total cell delay = 4.503 ns ( 36.88 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.706 ns ( 63.12 % ) " "Info: Total interconnect delay = 7.706 ns ( 63.12 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.209 ns" { clk count[10] Mux2~17 Mux2~18 Mux11~29 segdat_reg[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "12.209 ns" { clk {} clk~combout {} count[10] {} Mux2~17 {} Mux2~18 {} Mux11~29 {} segdat_reg[5] {} } { 0.000ns 0.000ns 1.267ns 0.000ns 0.305ns 1.744ns 4.390ns } { 0.000ns 1.163ns 1.294ns 0.595ns 0.200ns 0.740ns 0.511ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.005 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.005 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 24 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 24; CLK Node = 'clk'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 2 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns second 2 REG LC_X6_Y3_N8 10 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X6_Y3_N8; Fanout = 10; REG Node = 'second'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk second } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.321 ns) + CELL(1.294 ns) 8.339 ns cn 3 REG LC_X2_Y3_N2 8 " "Info: 3: + IC(3.321 ns) + CELL(1.294 ns) = 8.339 ns; Loc. = LC_X2_Y3_N2; Fanout = 8; REG Node = 'cn'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.615 ns" { second cn } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 13 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(0.918 ns) 12.005 ns min\[3\] 4 REG LC_X4_Y4_N7 4 " "Info: 4: + IC(2.748 ns) + CELL(0.918 ns) = 12.005 ns; Loc. = LC_X4_Y4_N7; Fanout = 4; REG Node = 'min\[3\]'" { } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.666 ns" { cn min[3] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 38.89 % ) " "Info: Total cell delay = 4.669 ns ( 38.89 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.336 ns ( 61.11 % ) " "Info: Total interconnect delay = 7.336 ns ( 61.11 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.005 ns" { clk second cn min[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "12.005 ns" { clk {} clk~combout {} second {} cn {} min[3] {} } { 0.000ns 0.000ns 1.267ns 3.321ns 2.748ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.209 ns" { clk count[10] Mux2~17 Mux2~18 Mux11~29 segdat_reg[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "12.209 ns" { clk {} clk~combout {} count[10] {} Mux2~17 {} Mux2~18 {} Mux11~29 {} segdat_reg[5] {} } { 0.000ns 0.000ns 1.267ns 0.000ns 0.305ns 1.744ns 4.390ns } { 0.000ns 1.163ns 1.294ns 0.595ns 0.200ns 0.740ns 0.511ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.005 ns" { clk second cn min[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "12.005 ns" { clk {} clk~combout {} second {} cn {} min[3] {} } { 0.000ns 0.000ns 1.267ns 3.321ns 2.748ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.115 ns + " "Info: + Micro setup delay of destination is 2.115 ns" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0} } { { "d:/program fi⌨️ 快捷键说明
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