prev_cmp_clock.qmsg

用Verilog HDL 实现时钟(时和分)

{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "segdat_reg\[0\] clock.v(36) " "Info (10041): Inferred latch for \"segdat_reg\[0\]\" at clock.v(36)" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "segdat_reg\[1\] clock.v(36) " "Info (10041): Inferred latch for \"segdat_reg\[1\]\" at clock.v(36)" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "segdat_reg\[2\] clock.v(36) " "Info (10041): Inferred latch for \"segdat_reg\[2\]\" at clock.v(36)" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "segdat_reg\[3\] clock.v(36) " "Info (10041): Inferred latch for \"segdat_reg\[3\]\" at clock.v(36)" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "segdat_reg\[4\] clock.v(36) " "Info (10041): Inferred latch for \"segdat_reg\[4\]\" at clock.v(36)" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "segdat_reg\[5\] clock.v(36) " "Info (10041): Inferred latch for \"segdat_reg\[5\]\" at clock.v(36)" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "segdat_reg\[6\] clock.v(36) " "Info (10041): Inferred latch for \"segdat_reg\[6\]\" at clock.v(36)" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "segdat_reg\[7\] clock.v(36) " "Info (10041): Inferred latch for \"segdat_reg\[7\]\" at clock.v(36)" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "fm~reg0 High " "Info: Power-up level of register \"fm~reg0\" is not specified -- using power-up level of High to minimize register" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 5 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0 "" 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "fm~reg0 data_in VCC " "Warning (14130): Reduced register \"fm~reg0\" with stuck data_in port to stuck value VCC" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 5 -1 0 } }  } 0 14130 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "segdat_reg\[0\] " "Warning: Latch segdat_reg\[0\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA count\[11\] " "Warning: Ports D and ENA on the latch are fed by the same signal count\[11\]" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "segdat_reg\[1\] " "Warning: Latch segdat_reg\[1\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA min\[2\] " "Warning: Ports D and ENA on the latch are fed by the same signal min\[2\]" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "segdat_reg\[2\] " "Warning: Latch segdat_reg\[2\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA count\[11\] " "Warning: Ports D and ENA on the latch are fed by the same signal count\[11\]" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "segdat_reg\[3\] " "Warning: Latch segdat_reg\[3\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA count\[11\] " "Warning: Ports D and ENA on the latch are fed by the same signal count\[11\]" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "segdat_reg\[4\] " "Warning: Latch segdat_reg\[4\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA count\[11\] " "Warning: Ports D and ENA on the latch are fed by the same signal count\[11\]" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "segdat_reg\[5\] " "Warning: Latch segdat_reg\[5\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA count\[11\] " "Warning: Ports D and ENA on the latch are fed by the same signal count\[11\]" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_UNSAFE_LATCH_HDR" "segdat_reg\[6\] " "Warning: Latch segdat_reg\[6\] has unsafe behavior" { { "Warning" "WOPT_MLS_UNSAFE_LATCH_SUB" "D ENA count\[11\] " "Warning: Ports D and ENA on the latch are fed by the same signal count\[11\]" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } }  } 0 0 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "" 0}  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Latch %1!s! has unsafe behavior" 0 0 "" 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "segdat\[7\] GND " "Warning (13410): Pin \"segdat\[7\]\" stuck at GND" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 3 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0} { "Warning" "WOPT_MLS_STUCK_PIN" "fm VCC " "Warning (13410): Pin \"fm\" stuck at VCC" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 5 -1 0 } }  } 0 13410 "Pin \"%1!s!\" stuck at %2!s!" 0 0 "" 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "117 " "Info: Implemented 117 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_OPINS" "15 " "Info: Implemented 15 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0} { "Info" "ICUT_CUT_TM_LCELLS" "101 " "Info: Implemented 101 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0}