📄 clock.tan.qmsg

📁 用Verilog HDL 实现时钟(时和分)
💻 QMSG
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register min\[3\] register segdat_reg\[5\] 68.57 MHz 14.584 ns Internal " "Info: Clock \"clk\" has Internal fmax of 68.57 MHz between source register \"min\[3\]\" and destination register \"segdat_reg\[5\]\" (period= 14.584 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.005 ns + Longest register register " "Info: + Longest register to register delay is 5.005 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns min\[3\] 1 REG LC_X4_Y4_N7 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N7; Fanout = 4; REG Node = 'min\[3\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { min[3] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.956 ns) + CELL(0.511 ns) 1.467 ns Mux0~28 2 COMB LC_X4_Y4_N1 1 " "Info: 2: + IC(0.956 ns) + CELL(0.511 ns) = 1.467 ns; Loc. = LC_X4_Y4_N1; Fanout = 1; COMB Node = 'Mux0~28'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.467 ns" { min[3] Mux0~28 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.727 ns) + CELL(0.200 ns) 2.394 ns Mux0~29 3 COMB LC_X4_Y4_N0 5 " "Info: 3: + IC(0.727 ns) + CELL(0.200 ns) = 2.394 ns; Loc. = LC_X4_Y4_N0; Fanout = 5; COMB Node = 'Mux0~29'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.927 ns" { Mux0~28 Mux0~29 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.906 ns) + CELL(0.200 ns) 4.500 ns Mux9~29 4 COMB LC_X2_Y4_N3 1 " "Info: 4: + IC(1.906 ns) + CELL(0.200 ns) = 4.500 ns; Loc. = LC_X2_Y4_N3; Fanout = 1; COMB Node = 'Mux9~29'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.106 ns" { Mux0~29 Mux9~29 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 5.005 ns segdat_reg\[5\] 5 REG LC_X2_Y4_N4 1 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 5.005 ns; Loc. = LC_X2_Y4_N4; Fanout = 1; REG Node = 'segdat_reg\[5\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { Mux9~29 segdat_reg[5] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.111 ns ( 22.20 % ) " "Info: Total cell delay = 1.111 ns ( 22.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.894 ns ( 77.80 % ) " "Info: Total interconnect delay = 3.894 ns ( 77.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.005 ns" { min[3] Mux0~28 Mux0~29 Mux9~29 segdat_reg[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.005 ns" { min[3] {} Mux0~28 {} Mux0~29 {} Mux9~29 {} segdat_reg[5] {} } { 0.000ns 0.956ns 0.727ns 1.906ns 0.305ns } { 0.000ns 0.511ns 0.200ns 0.200ns 0.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.204 ns - Smallest " "Info: - Smallest clock skew is 0.204 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.209 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 12.209 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 24 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 24; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns count\[10\] 2 REG LC_X4_Y4_N5 12 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X4_Y4_N5; Fanout = 12; REG Node = 'count\[10\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk count[10] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.595 ns) 4.319 ns Mux2~17 3 COMB LC_X4_Y4_N5 1 " "Info: 3: + IC(0.000 ns) + CELL(0.595 ns) = 4.319 ns; Loc. = LC_X4_Y4_N5; Fanout = 1; COMB Node = 'Mux2~17'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.595 ns" { count[10] Mux2~17 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 4.824 ns Mux2~18 4 COMB LC_X4_Y4_N6 8 " "Info: 4: + IC(0.305 ns) + CELL(0.200 ns) = 4.824 ns; Loc. = LC_X4_Y4_N6; Fanout = 8; COMB Node = 'Mux2~18'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { Mux2~17 Mux2~18 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.744 ns) + CELL(0.740 ns) 7.308 ns Mux11~29 5 COMB LC_X2_Y4_N6 7 " "Info: 5: + IC(1.744 ns) + CELL(0.740 ns) = 7.308 ns; Loc. = LC_X2_Y4_N6; Fanout = 7; COMB Node = 'Mux11~29'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.484 ns" { Mux2~18 Mux11~29 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.390 ns) + CELL(0.511 ns) 12.209 ns segdat_reg\[5\] 6 REG LC_X2_Y4_N4 1 " "Info: 6: + IC(4.390 ns) + CELL(0.511 ns) = 12.209 ns; Loc. = LC_X2_Y4_N4; Fanout = 1; REG Node = 'segdat_reg\[5\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.901 ns" { Mux11~29 segdat_reg[5] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.503 ns ( 36.88 % ) " "Info: Total cell delay = 4.503 ns ( 36.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.706 ns ( 63.12 % ) " "Info: Total interconnect delay = 7.706 ns ( 63.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.209 ns" { clk count[10] Mux2~17 Mux2~18 Mux11~29 segdat_reg[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "12.209 ns" { clk {} clk~combout {} count[10] {} Mux2~17 {} Mux2~18 {} Mux11~29 {} segdat_reg[5] {} } { 0.000ns 0.000ns 1.267ns 0.000ns 0.305ns 1.744ns 4.390ns } { 0.000ns 1.163ns 1.294ns 0.595ns 0.200ns 0.740ns 0.511ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.005 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.005 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 24 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 24; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns second 2 REG LC_X6_Y3_N8 10 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X6_Y3_N8; Fanout = 10; REG Node = 'second'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk second } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.321 ns) + CELL(1.294 ns) 8.339 ns cn 3 REG LC_X2_Y3_N2 8 " "Info: 3: + IC(3.321 ns) + CELL(1.294 ns) = 8.339 ns; Loc. = LC_X2_Y3_N2; Fanout = 8; REG Node = 'cn'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.615 ns" { second cn } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(0.918 ns) 12.005 ns min\[3\] 4 REG LC_X4_Y4_N7 4 " "Info: 4: + IC(2.748 ns) + CELL(0.918 ns) = 12.005 ns; Loc. = LC_X4_Y4_N7; Fanout = 4; REG Node = 'min\[3\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.666 ns" { cn min[3] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 38.89 % ) " "Info: Total cell delay = 4.669 ns ( 38.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.336 ns ( 61.11 % ) " "Info: Total interconnect delay = 7.336 ns ( 61.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.005 ns" { clk second cn min[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "12.005 ns" { clk {} clk~combout {} second {} cn {} min[3] {} } { 0.000ns 0.000ns 1.267ns 3.321ns 2.748ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.209 ns" { clk count[10] Mux2~17 Mux2~18 Mux11~29 segdat_reg[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "12.209 ns" { clk {} clk~combout {} count[10] {} Mux2~17 {} Mux2~18 {} Mux11~29 {} segdat_reg[5] {} } { 0.000ns 0.000ns 1.267ns 0.000ns 0.305ns 1.744ns 4.390ns } { 0.000ns 1.163ns 1.294ns 0.595ns 0.200ns 0.740ns 0.511ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.005 ns" { clk second cn min[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "12.005 ns" { clk {} clk~combout {} second {} cn {} min[3] {} } { 0.000ns 0.000ns 1.267ns 3.321ns 2.748ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.115 ns + " "Info: + Micro setup delay of destination is 2.115 ns" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.005 ns" { min[3] Mux0~28 Mux0~29 Mux9~29 segdat_reg[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.005 ns" { min[3] {} Mux0~28 {} Mux0~29 {} Mux9~29 {} segdat_reg[5] {} } { 0.000ns 0.956ns 0.727ns 1.906ns 0.305ns } { 0.000ns 0.511ns 0.200ns 0.200ns 0.200ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.209 ns" { clk count[10] Mux2~17 Mux2~18 Mux11~29 segdat_reg[5] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "12.209 ns" { clk {} clk~combout {} count[10] {} Mux2~17 {} Mux2~18 {} Mux11~29 {} segdat_reg[5] {} } { 0.000ns 0.000ns 1.267ns 0.000ns 0.305ns 1.744ns 4.390ns } { 0.000ns 1.163ns 1.294ns 0.595ns 0.200ns 0.740ns 0.511ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "12.005 ns" { clk second cn min[3] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "12.005 ns" { clk {} clk~combout {} second {} cn {} min[3] {} } { 0.000ns 0.000ns 1.267ns 3.321ns 2.748ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 114 " "Warning: Circuit may not operate. Detected 114 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "count\[10\] segdat_reg\[6\] clk 15.362 ns " "Info: Found hold time violation between source  pin or register \"count\[10\]\" and destination pin or register \"segdat_reg\[6\]\" for clock \"clk\" (Hold time is 15.362 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "18.673 ns + Largest " "Info: + Largest clock skew is 18.673 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 22.021 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 22.021 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 24 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 24; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns second 2 REG LC_X6_Y3_N8 10 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X6_Y3_N8; Fanout = 10; REG Node = 'second'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk second } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.321 ns) + CELL(1.294 ns) 8.339 ns cn 3 REG LC_X2_Y3_N2 8 " "Info: 3: + IC(3.321 ns) + CELL(1.294 ns) = 8.339 ns; Loc. = LC_X2_Y3_N2; Fanout = 8; REG Node = 'cn'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.615 ns" { second cn } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(1.294 ns) 12.381 ns min\[3\] 4 REG LC_X4_Y4_N7 4 " "Info: 4: + IC(2.748 ns) + CELL(1.294 ns) = 12.381 ns; Loc. = LC_X4_Y4_N7; Fanout = 4; REG Node = 'min\[3\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.042 ns" { cn min[3] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.956 ns) + CELL(0.511 ns) 13.848 ns Mux0~28 5 COMB LC_X4_Y4_N1 1 " "Info: 5: + IC(0.956 ns) + CELL(0.511 ns) = 13.848 ns; Loc. = LC_X4_Y4_N1; Fanout = 1; COMB Node = 'Mux0~28'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.467 ns" { min[3] Mux0~28 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.727 ns) + CELL(0.200 ns) 14.775 ns Mux0~29 6 COMB LC_X4_Y4_N0 5 " "Info: 6: + IC(0.727 ns) + CELL(0.200 ns) = 14.775 ns; Loc. = LC_X4_Y4_N0; Fanout = 5; COMB Node = 'Mux0~29'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.927 ns" { Mux0~28 Mux0~29 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.870 ns) + CELL(0.511 ns) 17.156 ns Mux11~29 7 COMB LC_X2_Y4_N6 7 " "Info: 7: + IC(1.870 ns) + CELL(0.511 ns) = 17.156 ns; Loc. = LC_X2_Y4_N6; Fanout = 7; COMB Node = 'Mux11~29'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.381 ns" { Mux0~29 Mux11~29 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.354 ns) + CELL(0.511 ns) 22.021 ns segdat_reg\[6\] 8 REG LC_X4_Y4_N4 1 " "Info: 8: + IC(4.354 ns) + CELL(0.511 ns) = 22.021 ns; Loc. = LC_X4_Y4_N4; Fanout = 1; REG Node = 'segdat_reg\[6\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.865 ns" { Mux11~29 segdat_reg[6] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.778 ns ( 30.78 % ) " "Info: Total cell delay = 6.778 ns ( 30.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.243 ns ( 69.22 % ) " "Info: Total interconnect delay = 15.243 ns ( 69.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "22.021 ns" { clk second cn min[3] Mux0~28 Mux0~29 Mux11~29 segdat_reg[6] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "22.021 ns" { clk {} clk~combout {} second {} cn {} min[3] {} Mux0~28 {} Mux0~29 {} Mux11~29 {} segdat_reg[6] {} } { 0.000ns 0.000ns 1.267ns 3.321ns 2.748ns 0.956ns 0.727ns 1.870ns 4.354ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.511ns 0.200ns 0.511ns 0.511ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 24 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 24; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns count\[10\] 2 REG LC_X4_Y4_N5 12 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X4_Y4_N5; Fanout = 12; REG Node = 'count\[10\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk count[10] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk count[10] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} count[10] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "22.021 ns" { clk second cn min[3] Mux0~28 Mux0~29 Mux11~29 segdat_reg[6] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "22.021 ns" { clk {} clk~combout {} second {} cn {} min[3] {} Mux0~28 {} Mux0~29 {} Mux11~29 {} segdat_reg[6] {} } { 0.000ns 0.000ns 1.267ns 3.321ns 2.748ns 0.956ns 0.727ns 1.870ns 4.354ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.511ns 0.200ns 0.511ns 0.511ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk count[10] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} count[10] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns - " "Info: - Micro clock to output delay of source is 0.376 ns" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.935 ns - Shortest register register " "Info: - Shortest register to register delay is 2.935 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count\[10\] 1 REG LC_X4_Y4_N5 12 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N5; Fanout = 12; REG Node = 'count\[10\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { count[10] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.595 ns) 0.595 ns Mux2~17 2 COMB LC_X4_Y4_N5 1 " "Info: 2: + IC(0.000 ns) + CELL(0.595 ns) = 0.595 ns; Loc. = LC_X4_Y4_N5; Fanout = 1; COMB Node = 'Mux2~17'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.595 ns" { count[10] Mux2~17 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 1.100 ns Mux2~18 3 COMB LC_X4_Y4_N6 8 " "Info: 3: + IC(0.305 ns) + CELL(0.200 ns) = 1.100 ns; Loc. = LC_X4_Y4_N6; Fanout = 8; COMB Node = 'Mux2~18'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { Mux2~17 Mux2~18 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.819 ns) + CELL(0.511 ns) 2.430 ns Mux10~30 4 COMB LC_X4_Y4_N3 1 " "Info: 4: + IC(0.819 ns) + CELL(0.511 ns) = 2.430 ns; Loc. = LC_X4_Y4_N3; Fanout = 1; COMB Node = 'Mux10~30'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.330 ns" { Mux2~18 Mux10~30 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.305 ns) + CELL(0.200 ns) 2.935 ns segdat_reg\[6\] 5 REG LC_X4_Y4_N4 1 " "Info: 5: + IC(0.305 ns) + CELL(0.200 ns) = 2.935 ns; Loc. = LC_X4_Y4_N4; Fanout = 1; REG Node = 'segdat_reg\[6\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.505 ns" { Mux10~30 segdat_reg[6] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.506 ns ( 51.31 % ) " "Info: Total cell delay = 1.506 ns ( 51.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.429 ns ( 48.69 % ) " "Info: Total interconnect delay = 1.429 ns ( 48.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.935 ns" { count[10] Mux2~17 Mux2~18 Mux10~30 segdat_reg[6] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.935 ns" { count[10] {} Mux2~17 {} Mux2~18 {} Mux10~30 {} segdat_reg[6] {} } { 0.000ns 0.000ns 0.305ns 0.819ns 0.305ns } { 0.000ns 0.595ns 0.200ns 0.511ns 0.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "22.021 ns" { clk second cn min[3] Mux0~28 Mux0~29 Mux11~29 segdat_reg[6] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "22.021 ns" { clk {} clk~combout {} second {} cn {} min[3] {} Mux0~28 {} Mux0~29 {} Mux11~29 {} segdat_reg[6] {} } { 0.000ns 0.000ns 1.267ns 3.321ns 2.748ns 0.956ns 0.727ns 1.870ns 4.354ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.511ns 0.200ns 0.511ns 0.511ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk count[10] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk {} clk~combout {} count[10] {} } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.935 ns" { count[10] Mux2~17 Mux2~18 Mux10~30 segdat_reg[6] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.935 ns" { count[10] {} Mux2~17 {} Mux2~18 {} Mux10~30 {} segdat_reg[6] {} } { 0.000ns 0.000ns 0.305ns 0.819ns 0.305ns } { 0.000ns 0.595ns 0.200ns 0.511ns 0.200ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk segdat\[0\] segdat_reg\[0\] 26.587 ns register " "Info: tco from clock \"clk\" to destination pin \"segdat\[0\]\" through register \"segdat_reg\[0\]\" is 26.587 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 22.019 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 22.019 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 24 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 24; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns second 2 REG LC_X6_Y3_N8 10 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X6_Y3_N8; Fanout = 10; REG Node = 'second'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk second } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.321 ns) + CELL(1.294 ns) 8.339 ns cn 3 REG LC_X2_Y3_N2 8 " "Info: 3: + IC(3.321 ns) + CELL(1.294 ns) = 8.339 ns; Loc. = LC_X2_Y3_N2; Fanout = 8; REG Node = 'cn'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.615 ns" { second cn } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 13 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.748 ns) + CELL(1.294 ns) 12.381 ns min\[3\] 4 REG LC_X4_Y4_N7 4 " "Info: 4: + IC(2.748 ns) + CELL(1.294 ns) = 12.381 ns; Loc. = LC_X4_Y4_N7; Fanout = 4; REG Node = 'min\[3\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.042 ns" { cn min[3] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.956 ns) + CELL(0.511 ns) 13.848 ns Mux0~28 5 COMB LC_X4_Y4_N1 1 " "Info: 5: + IC(0.956 ns) + CELL(0.511 ns) = 13.848 ns; Loc. = LC_X4_Y4_N1; Fanout = 1; COMB Node = 'Mux0~28'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.467 ns" { min[3] Mux0~28 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.727 ns) + CELL(0.200 ns) 14.775 ns Mux0~29 6 COMB LC_X4_Y4_N0 5 " "Info: 6: + IC(0.727 ns) + CELL(0.200 ns) = 14.775 ns; Loc. = LC_X4_Y4_N0; Fanout = 5; COMB Node = 'Mux0~29'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "0.927 ns" { Mux0~28 Mux0~29 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.870 ns) + CELL(0.511 ns) 17.156 ns Mux11~29 7 COMB LC_X2_Y4_N6 7 " "Info: 7: + IC(1.870 ns) + CELL(0.511 ns) = 17.156 ns; Loc. = LC_X2_Y4_N6; Fanout = 7; COMB Node = 'Mux11~29'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.381 ns" { Mux0~29 Mux11~29 } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.352 ns) + CELL(0.511 ns) 22.019 ns segdat_reg\[0\] 8 REG LC_X4_Y4_N9 1 " "Info: 8: + IC(4.352 ns) + CELL(0.511 ns) = 22.019 ns; Loc. = LC_X4_Y4_N9; Fanout = 1; REG Node = 'segdat_reg\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.863 ns" { Mux11~29 segdat_reg[0] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.778 ns ( 30.78 % ) " "Info: Total cell delay = 6.778 ns ( 30.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "15.241 ns ( 69.22 % ) " "Info: Total interconnect delay = 15.241 ns ( 69.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "22.019 ns" { clk second cn min[3] Mux0~28 Mux0~29 Mux11~29 segdat_reg[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "22.019 ns" { clk {} clk~combout {} second {} cn {} min[3] {} Mux0~28 {} Mux0~29 {} Mux11~29 {} segdat_reg[0] {} } { 0.000ns 0.000ns 1.267ns 3.321ns 2.748ns 0.956ns 0.727ns 1.870ns 4.352ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.511ns 0.200ns 0.511ns 0.511ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.568 ns + Longest register pin " "Info: + Longest register to pin delay is 4.568 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns segdat_reg\[0\] 1 REG LC_X4_Y4_N9 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X4_Y4_N9; Fanout = 1; REG Node = 'segdat_reg\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { segdat_reg[0] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.246 ns) + CELL(2.322 ns) 4.568 ns segdat\[0\] 2 PIN PIN_99 0 " "Info: 2: + IC(2.246 ns) + CELL(2.322 ns) = 4.568 ns; Loc. = PIN_99; Fanout = 0; PIN Node = 'segdat\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.568 ns" { segdat_reg[0] segdat[0] } "NODE_NAME" } } { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 50.83 % ) " "Info: Total cell delay = 2.322 ns ( 50.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.246 ns ( 49.17 % ) " "Info: Total interconnect delay = 2.246 ns ( 49.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.568 ns" { segdat_reg[0] segdat[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.568 ns" { segdat_reg[0] {} segdat[0] {} } { 0.000ns 2.246ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "22.019 ns" { clk second cn min[3] Mux0~28 Mux0~29 Mux11~29 segdat_reg[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "22.019 ns" { clk {} clk~combout {} second {} cn {} min[3] {} Mux0~28 {} Mux0~29 {} Mux11~29 {} segdat_reg[0] {} } { 0.000ns 0.000ns 1.267ns 3.321ns 2.748ns 0.956ns 0.727ns 1.870ns 4.352ns } { 0.000ns 1.163ns 1.294ns 1.294ns 1.294ns 0.511ns 0.200ns 0.511ns 0.511ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "4.568 ns" { segdat_reg[0] segdat[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "4.568 ns" { segdat_reg[0] {} segdat[0] {} } { 0.000ns 2.246ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
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