clock.tan.qmsg

用Verilog HDL 实现时钟(时和分)

{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "segdat_reg\[0\] " "Warning: Node \"segdat_reg\[0\]\" is a latch" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segdat_reg\[1\] " "Warning: Node \"segdat_reg\[1\]\" is a latch" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segdat_reg\[2\] " "Warning: Node \"segdat_reg\[2\]\" is a latch" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segdat_reg\[3\] " "Warning: Node \"segdat_reg\[3\]\" is a latch" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segdat_reg\[4\] " "Warning: Node \"segdat_reg\[4\]\" is a latch" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segdat_reg\[5\] " "Warning: Node \"segdat_reg\[5\]\" is a latch" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "segdat_reg\[6\] " "Warning: Node \"segdat_reg\[6\]\" is a latch" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 36 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 2 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "22 " "Warning: Found 22 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Mux0~29 " "Info: Detected gated clock \"Mux0~29\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux0~29" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux0~28 " "Info: Detected gated clock \"Mux0~28\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux0~28" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux1~28 " "Info: Detected gated clock \"Mux1~28\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux1~28" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux1~27 " "Info: Detected gated clock \"Mux1~27\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux1~27" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux2~18 " "Info: Detected gated clock \"Mux2~18\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux2~18" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "min\[6\] " "Info: Detected ripple clock \"min\[6\]\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "min\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "min\[7\] " "Info: Detected ripple clock \"min\[7\]\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "min\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "min\[5\] " "Info: Detected ripple clock \"min\[5\]\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "min\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux2~17 " "Info: Detected gated clock \"Mux2~17\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 28 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux2~17" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "min\[3\] " "Info: Detected ripple clock \"min\[3\]\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "min\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "min\[2\] " "Info: Detected ripple clock \"min\[2\]\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "min\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "min\[1\] " "Info: Detected ripple clock \"min\[1\]\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 78 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "min\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sec\[6\] " "Info: Detected ripple clock \"sec\[6\]\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 62 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sec\[6\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sec\[7\] " "Info: Detected ripple clock \"sec\[7\]\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 62 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sec\[7\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sec\[5\] " "Info: Detected ripple clock \"sec\[5\]\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 62 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sec\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sec\[1\] " "Info: Detected ripple clock \"sec\[1\]\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 62 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sec\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sec\[3\] " "Info: Detected ripple clock \"sec\[3\]\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 62 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sec\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sec\[2\] " "Info: Detected ripple clock \"sec\[2\]\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 62 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "sec\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "second " "Info: Detected ripple clock \"second\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 12 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "second" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "cn " "Info: Detected ripple clock \"cn\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 13 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "cn" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count\[10\] " "Info: Detected ripple clock \"count\[10\]\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count\[10\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count\[11\] " "Info: Detected ripple clock \"count\[11\]\" as buffer" {  } { { "clock.v" "" { Text "F:/yam/study/CPLD FPGA/CPLD/Verilong HDL/Text/Quartus II/clock/clock.v" 15 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "count\[11\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}