clock.tan.summary

来自「用Verilog HDL 实现时钟(时和分)」· SUMMARY 代码 · 共 47 行

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Timing Analyzer Summary
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Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 26.587 ns
From           : segdat_reg[0]
To             : segdat[0]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 68.57 MHz ( period = 14.584 ns )
From           : min[3]
To             : segdat_reg[5]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : count[10]
To             : segdat_reg[6]
From Clock     : clk
To Clock       : clk
Failed Paths   : 114

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 114

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