clock.v.bak

用Verilog HDL 实现时钟(时和分)

module clock(clk,segdat,sl,fm);
input clk;
output[7:0] segdat;
output[5:0] sl;
output fm;
reg fm;
reg[22:0] count;
reg[7:0] sec,min;
reg[7:0] segdat_reg;
reg[5:0] sl_reg;
reg[3:0] disp_dat;
reg second;
reg cn;

always @(posedge clk)
begin	
	fm=1;
	count=count+1;
	if(count==23'd5529630)
	begin
		count=23'h000000;
		second=~second;
	end
end

always @(count[11:10])
begin
	case(count[11:10])
	2'b00:disp_dat=sec[3:0];
	2'b01:disp_dat=sec[7:4];
	2'b10:disp_dat=min[3:0];
	2'b11:disp_dat=min[7:4];
	endcase
end

always @(disp_dat)
begin
	case(disp_dat)
	4'h0:segdat_reg=8'h3f;
	4'h1:segdat_reg=8'h06;
	4'h2:segdat_reg=8'h5b;
	4'h3:segdat_reg=8'h4f;
	4'h4:segdat_reg=8'h66;
	4'h5:segdat_reg=8'h6d;
	4'h6:segdat_reg=8'h7d;
	4'h7:segdat_reg=8'h07;
	4'h8:segdat_reg=8'h7f;
	4'h9:segdat_reg=8'h6f;
	endcase
end

always @(count[11:10])
begin
	case(count[11:10])
	2'b00:sl_reg=6'b111110;
	2'b01:sl_reg=4'b111101;
	2'b10:sl_reg=4'b111011;
	2'b11:sl_reg=4'b110111;
	endcase
end

always @(posedge second)
begin
	cn=0;
	sec[3:0]=sec[3:0]+1;
	if(sec[3:0]==4'd10)
		begin
			sec[3:0]=4'd0;
			sec[7:4]=sec[7:4]+1;
			if(sec[7:4]==4'd6)
				begin
					sec[7:4]=0;
					cn=1;
				end
		end
end

always @(posedge cn)
begin
	min[3:0]=min[3:0]+1;
	if(min[3:0]==4'd10)
		begin
			min[3:0]=4'd0;
			min[7:4]=min[7:4]+1;
			if(min[7:4]==4'd6)
				min[7:4]=4'd0;
		end
end

assign segdat=segdat_reg;
assign sl=sl_reg;
endmodule