clock.map.rpt

用Verilog HDL 实现时钟(时和分)

;     -- 0 input functions                    ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 79    ;
;     -- arithmetic mode                      ; 22    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 41    ;
; Total logic cells in carry chains           ; 23    ;
; I/O pins                                    ; 16    ;
; Maximum fan-out node                        ; clk   ;
; Maximum fan-out                             ; 24    ;
; Total fan-out                               ; 330   ;
; Average fan-out                             ; 2.82  ;
+---------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
; |clock                     ; 101 (101)   ; 41           ; 0           ; 0            ; 0       ; 0         ; 0         ; 16   ; 0            ; 60 (60)      ; 14 (14)           ; 27 (27)          ; 23 (23)         ; 0 (0)      ; |clock              ; work         ;
+----------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; segdat_reg[0]                                      ; Mux11               ; yes                    ;
; segdat_reg[1]                                      ; Mux11               ; yes                    ;
; segdat_reg[2]                                      ; Mux11               ; yes                    ;
; segdat_reg[3]                                      ; Mux11               ; yes                    ;
; segdat_reg[4]                                      ; Mux11               ; yes                    ;
; segdat_reg[5]                                      ; Mux11               ; yes                    ;
; segdat_reg[6]                                      ; Mux11               ; yes                    ;
; Number of user-specified and inferred latches = 7  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                             ;
+---------------------------------------+----------------------------------------+
; Register name                         ; Reason for Removal                     ;
+---------------------------------------+----------------------------------------+
; fm~reg0                               ; Stuck at VCC due to stuck port data_in ;
; Total Number of Removed Registers = 1 ;                                        ;
+---------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 41    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 8     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |clock|Mux0                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Tue Jan 20 14:09:58 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off clock -c clock
Info: Found 1 design units, including 1 entities, in source file clock.v
    Info: Found entity 1: clock
Info: Elaborating entity "clock" for the top level hierarchy
Warning (10230): Verilog HDL assignment warning at clock.v(18): truncated value with size 32 to match size of target (23)
Warning (10235): Verilog HDL Always Construct warning at clock.v(29): variable "sec" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at clock.v(30): variable "sec" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at clock.v(31): variable "min" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at clock.v(32): variable "min" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10270): Verilog HDL Case Statement warning at clock.v(38): incomplete case statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at clock.v(36): inferring latch(es) for variable "segdat_reg", which holds its previous value in one or more paths through the always construct
Warning (10230): Verilog HDL assignment warning at clock.v(65): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(69): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(80): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at clock.v(84): truncated value with size 32 to match size of target (4)
Info (10041): Inferred latch for "segdat_reg[0]" at clock.v(36)
Info (10041): Inferred latch for "segdat_reg[1]" at clock.v(36)
Info (10041): Inferred latch for "segdat_reg[2]" at clock.v(36)
Info (10041): Inferred latch for "segdat_reg[3]" at clock.v(36)
Info (10041): Inferred latch for "segdat_reg[4]" at clock.v(36)
Info (10041): Inferred latch for "segdat_reg[5]" at clock.v(36)
Info (10041): Inferred latch for "segdat_reg[6]" at clock.v(36)
Info (10041): Inferred latch for "segdat_reg[7]" at clock.v(36)
Info: Power-up level of register "fm~reg0" is not specified -- using power-up level of High to minimize register
Warning (14130): Reduced register "fm~reg0" with stuck data_in port to stuck value VCC
Warning: Latch segdat_reg[0] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal count[11]
Warning: Latch segdat_reg[1] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal min[2]
Warning: Latch segdat_reg[2] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal count[11]
Warning: Latch segdat_reg[3] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal count[11]
Warning: Latch segdat_reg[4] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal count[11]
Warning: Latch segdat_reg[5] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal count[11]
Warning: Latch segdat_reg[6] has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal count[11]
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "segdat[7]" stuck at GND
    Warning (13410): Pin "sl[4]" stuck at VCC
    Warning (13410): Pin "sl[5]" stuck at VCC
    Warning (13410): Pin "fm" stuck at VCC
Info: Implemented 117 device resources after synthesis - the final resource count might be different
    Info: Implemented 1 input pins
    Info: Implemented 15 output pins
    Info: Implemented 101 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 31 warnings
    Info: Allocated 142 megabytes of memory during processing
    Info: Processing ended: Tue Jan 20 14:10:04 2009
    Info: Elapsed time: 00:00:06