prev_cmp_beep.map.qmsg

verilog写的控制喇叭的FPGA程序。

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version " "Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Jan 06 11:53:29 2009 " "Info: Processing started: Tue Jan 06 11:53:29 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off beep -c beep " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off beep -c beep" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "beep.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file beep.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 beep " "Info: Found entity 1: beep" {  } { { "beep.bdf" "" { Schematic "D:/FPGA/verilongsample/beep/beep.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "22 buzzer.v(52) " "Warning (10229): Verilog HDL Expression warning at buzzer.v(52): truncated literal to match 22 bits" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 52 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "22 buzzer.v(63) " "Warning (10229): Verilog HDL Expression warning at buzzer.v(63): truncated literal to match 22 bits" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 63 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "22 buzzer.v(74) " "Warning (10229): Verilog HDL Expression warning at buzzer.v(74): truncated literal to match 22 bits" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 74 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "22 buzzer.v(85) " "Warning (10229): Verilog HDL Expression warning at buzzer.v(85): truncated literal to match 22 bits" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 85 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "22 buzzer.v(96) " "Warning (10229): Verilog HDL Expression warning at buzzer.v(96): truncated literal to match 22 bits" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 96 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "22 buzzer.v(107) " "Warning (10229): Verilog HDL Expression warning at buzzer.v(107): truncated literal to match 22 bits" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 107 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "22 buzzer.v(118) " "Warning (10229): Verilog HDL Expression warning at buzzer.v(118): truncated literal to match 22 bits" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 118 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "22 buzzer.v(129) " "Warning (10229): Verilog HDL Expression warning at buzzer.v(129): truncated literal to match 22 bits" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 129 0 0 } }  } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "buzzer.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file buzzer.v" { { "Info" "ISGN_ENTITY_NAME" "1 buzzer " "Info: Found entity 1: buzzer" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "beep " "Info: Elaborating entity \"beep\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PROCESSING_LEGACY_SCHEMATIC_WITH_MAXPLUS_II_NAMING" "beep " "Warning: Processing legacy GDF or BDF entity \"beep\" with Max+Plus II bus and instance naming rules" {  } { { "beep.bdf" "" { Schematic "D:/FPGA/verilongsample/beep/beep.bdf" { } } }  } 0 0 "Processing legacy GDF or BDF entity \"%1!s!\" with Max+Plus II bus and instance naming rules" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "buzzer buzzer:inst " "Info: Elaborating entity \"buzzer\" for hierarchy \"buzzer:inst\"" {  } { { "beep.bdf" "inst" { Schematic "D:/FPGA/verilongsample/beep/beep.bdf" { { 136 312 408 232 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(51) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(51): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 51 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(55) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(55): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 55 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 22 buzzer.v(62) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(62): truncated value with size 32 to match size of target (22)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 62 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 buzzer.v(66) " "Warning (10230): Verilog HDL assignment warning at buzzer.v(66): truncated value with size 32 to match size of target (13)" {  } { { "buzzer.v" "" { Text "D:/FPGA/verilongsample/beep/buzzer.v" 66 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}