beep.map.summary

来自「verilog写的控制喇叭的FPGA程序。」· SUMMARY 代码 · 共 15 行

Analysis & Synthesis Status : Successful - Tue Jan 06 11:55:05 2009
Quartus II Version : 7.2 Build 207 03/18/2008 SP 3 SJ Full Version
Revision Name : beep
Top-level Entity Name : beep
Family : Cyclone II
Total logic elements : 110
    Total combinational functions : 110
    Dedicated logic registers : 48
Total registers : 48
Total pins : 3
Total virtual pins : 0
Total memory bits : 0
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0