displayl.vhd

在 Quartus II 7.1平台下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity displayl is
  port(datainl:in std_logic_vector(3 downto 0);      --连接segmain扫描部分信号
		ldata_out:out std_logic_vector(6 downto 0));  --输出段选
		
end displayl;
architecture playl of displayl is
  begin
    process(datainl) is
		begin
		case datainl is
		--when "0000"=>ldata_out<="1000000";  --显示0
		--when "0001"=>ldata_out<="1111001";  --显示1  
		--when "0010"=>ldata_out<="0100100";  --显示2
		--when "0011"=>ldata_out<="0110000";  --显示3
		--when "0100"=>ldata_out<="0011001";  --显示4
		--when "0101"=>ldata_out<="0010010";  --显示5
		--when "0110"=>ldata_out<="0000010";  --显示6
		--when "0111"=>ldata_out<="1111000";  --显示7
		--when "1000"=>ldata_out<="0000000";  --显示8
		--when others=>ldata_out<="0010000";  --显示9
		when "0000"=>ldata_out<="1000000";  --显示0
		when "0001"=>ldata_out<="1001111";  --显示1  
		when "0010"=>ldata_out<="0100100";  --显示2
		when "0011"=>ldata_out<="0000110";  --显示3
		when "0100"=>ldata_out<="0001011";  --显示4
		when "0101"=>ldata_out<="0010010";  --显示5
		when "0110"=>ldata_out<="0010000";  --显示6
		when "0111"=>ldata_out<="1000111";  --显示7
		when "1000"=>ldata_out<="0000000";  --显示8
		when others=>ldata_out<="0000010";  --显示9
		end case;
	end process;
end architecture ;