cnt6.vhd

来自「在 Quartus II 7.1平台下」· VHDL 代码 · 共 32 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt6 is
       port(clk :in std_logic;
            ena :in std_logic;
            clr :in std_logic;
              cq :out std_logic_vector(3 downto 0);
           outy :out std_logic );
end;
architecture behave of cnt6 is
   signal cqi :std_logic_vector(3 downto 0);
begin
process (clk,clr,ena)
begin
     if clr = '1' then cqi <="0000";
     elsif clk'event and clk='1' then
        if ena ='1' then 
            if cqi="0101" then cqi<="0000";
            else cqi <= cqi+1;
            end if;
         end if;
     end if;
cq<= cqi;
end process;
process(cqi)
  begin 
   if cqi="0000" then outy<='1';
   else outy<='0';
   end if;
  end process;
end;