clkgen1.vhd

来自「在 Quartus II 7.1平台下」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity clkgen1 is
	port(clk:in std_logic;
		newclk1:out std_logic);
end clkgen1;
architecture art of clkgen1 is
signal cnter:integer range 0 to 10#699999#;  --十进制计数预制数
  begin
	process(clk) is
	 begin
	if clk'event and clk='1' then
	   if cnter=10#699999# then        --50MHZ变为100HZ，计数常数为50000
	      cnter<=0;
	   else cnter<=cnter+1;
	   end if;
	end if;
	end process;
   process(cnter) is         --计数溢出信号控制
    begin
	 if cnter=10#699999# then
	  newclk1<='1';
	 else newclk1<='0';
	end if;
	end process;
end architecture art;