segmain.vhd

在 Quartus II 7.1平台下

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity segmain is
port(clk:in std_logic;
	 clr:in std_logic;
	msec0,msec1,sec0,sec1,min0,min1:
	in std_logic_vector(3 downto 0);       --输入,分别为微秒个、时位，秒个位/时位；分个位/时位
	hdataout:out std_logic_vector(3 downto 0);     --输出
	ldataout:out std_logic_vector(3 downto 0);     --输出
	ledcom: out std_logic_vector(7 downto 0));    --位选
end segmain;
architecture behave of segmain is
  signal comclk:integer range 0 to 5;       --内部计数信号
signal lout,hout :std_logic_vector(3 downto 0); 
begin

 process(clr,clk) is
   begin
	if clr='1' then
	    hout<="0000";
		lout<="0000";
		ledcom<="11000000";
		comclk<=0;
	elsif rising_edge(clk)then
		if comclk>=5 then
			comclk<=0;
		else 
		comclk<=comclk+1;
		end if;
    case comclk is
    when 0=>ledcom<="11111110";lout<=msec0;
	when 1=>ledcom<="11111101";lout<=msec1;
	when 2=>ledcom<="11111011";lout<=sec0;
	when 3=>ledcom<="11110111";lout<=sec1;
	when 4=>ledcom<="11101111";hout<=min0;
	when 5=>ledcom<="11011111";hout<=min1;
	end case;
	end if;
	ldataout<=lout;
	hdataout<=hout;
  end process;
end architecture behave;