miaobiao.map.rpt

在 Quartus II 7.1平台下

;     -- 4 input functions                    ; 55    ;
;     -- 3 input functions                    ; 9     ;
;     -- 2 input functions                    ; 57    ;
;     -- 1 input functions                    ; 7     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 112   ;
;     -- arithmetic mode                      ; 33    ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 41    ;
;                                             ;       ;
; Total registers                             ; 73    ;
; Total logic cells in carry chains           ; 35    ;
; I/O pins                                    ; 27    ;
; Maximum fan-out node                        ; clr   ;
; Maximum fan-out                             ; 41    ;
; Total fan-out                               ; 545   ;
; Average fan-out                             ; 3.17  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                          ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name       ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------+
; |miaobiao                  ; 145 (16)    ; 73           ; 0           ; 27   ; 0            ; 72 (16)      ; 17 (0)            ; 56 (0)           ; 35 (0)          ; 0 (0)      ; |miaobiao                 ;
;    |clkgen1:inst1|         ; 35 (35)     ; 16           ; 0           ; 0    ; 0            ; 19 (19)      ; 7 (7)             ; 9 (9)            ; 19 (19)         ; 0 (0)      ; |miaobiao|clkgen1:inst1   ;
;    |clkgen2:inst|          ; 32 (32)     ; 16           ; 0           ; 0    ; 0            ; 16 (16)      ; 10 (10)           ; 6 (6)            ; 16 (16)         ; 0 (0)      ; |miaobiao|clkgen2:inst    ;
;    |cnt10:inst2|           ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |miaobiao|cnt10:inst2     ;
;    |cnt10:inst7|           ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |miaobiao|cnt10:inst7     ;
;    |cnt10:inst8|           ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |miaobiao|cnt10:inst8     ;
;    |cnt10:inst9|           ; 4 (4)       ; 4            ; 0           ; 0    ; 0            ; 0 (0)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |miaobiao|cnt10:inst9     ;
;    |cnt6:inst10|           ; 5 (5)       ; 4            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |miaobiao|cnt6:inst10     ;
;    |cnt6:inst3|            ; 5 (5)       ; 4            ; 0           ; 0    ; 0            ; 1 (1)        ; 0 (0)             ; 4 (4)            ; 0 (0)           ; 0 (0)      ; |miaobiao|cnt6:inst3      ;
;    |displayh:inst11|       ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |miaobiao|displayh:inst11 ;
;    |displayl:inst4|        ; 7 (7)       ; 0            ; 0           ; 0    ; 0            ; 7 (7)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |miaobiao|displayl:inst4  ;
;    |segmain:inst6|         ; 22 (22)     ; 17           ; 0           ; 0    ; 0            ; 5 (5)        ; 0 (0)             ; 17 (17)          ; 0 (0)           ; 0 (0)      ; |miaobiao|segmain:inst6   ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 73    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 41    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 26    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |miaobiao|segmain:inst6|hout[0] ;
; 6:1                ; 4 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |miaobiao|segmain:inst6|lout[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/finishedmb/miaobiao.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon Jan 14 08:05:15 2002
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off miaobiao -c miaobiao
Info: Found 1 design units, including 1 entities, in source file miaobiao.bdf
    Info: Found entity 1: miaobiao
Info: Found 2 design units, including 1 entities, in source file segmain.vhd
    Info: Found design unit 1: segmain-behave
    Info: Found entity 1: segmain
Info: Found 2 design units, including 1 entities, in source file clkgen1.vhd
    Info: Found design unit 1: clkgen1-art
    Info: Found entity 1: clkgen1
Info: Found 2 design units, including 1 entities, in source file clkgen2.vhd
    Info: Found design unit 1: clkgen2-art
    Info: Found entity 1: clkgen2
Info: Found 2 design units, including 1 entities, in source file cnt6.vhd
    Info: Found design unit 1: cnt6-behave
    Info: Found entity 1: cnt6
Info: Found 2 design units, including 1 entities, in source file cnt10.vhd
    Info: Found design unit 1: cnt10-art
    Info: Found entity 1: cnt10
Info: Found 2 design units, including 1 entities, in source file displayh.vhd
    Info: Found design unit 1: displayh-playh
    Info: Found entity 1: displayh
Info: Found 2 design units, including 1 entities, in source file displayl.vhd
    Info: Found design unit 1: displayl-playl
    Info: Found entity 1: displayl
Info: Elaborating entity "miaobiao" for the top level hierarchy
Info: Elaborating entity "displayh" for hierarchy "displayh:inst11"
Info: Elaborating entity "segmain" for hierarchy "segmain:inst6"
Warning (10492): VHDL Process Statement warning at segmain.vhd(40): signal "lout" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at segmain.vhd(41): signal "hout" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "clkgen2" for hierarchy "clkgen2:inst"
Info: Elaborating entity "cnt10" for hierarchy "cnt10:inst9"
Info: Elaborating entity "cnt6" for hierarchy "cnt6:inst3"
Warning (10492): VHDL Process Statement warning at cnt6.vhd(24): signal "cqi" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Elaborating entity "clkgen1" for hierarchy "clkgen1:inst1"
Info: Elaborating entity "displayl" for hierarchy "displayl:inst4"
Info: Power-up level of register "segmain:inst6|ledcom[7]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "segmain:inst6|ledcom[7]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "segmain:inst6|ledcom[6]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "segmain:inst6|ledcom[6]" with stuck data_in port to stuck value VCC
Info: Duplicate registers merged to single register
    Info: Duplicate register "clkgen1:inst1|cnter[0]" merged to single register "clkgen2:inst|cnter[0]"
    Info: Duplicate register "clkgen1:inst1|cnter[1]" merged to single register "clkgen2:inst|cnter[1]"
Info: Duplicate registers merged to single register
    Info: Duplicate register "clkgen1:inst1|cnter[2]" merged to single register "clkgen2:inst|cnter[2]"
    Info: Duplicate register "clkgen1:inst1|cnter[3]" merged to single register "clkgen2:inst|cnter[3]"
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "ledcom[7]" stuck at VCC
    Warning: Pin "ledcom[6]" stuck at VCC
    Warning: Pin "zero[1]" stuck at VCC
    Warning: Pin "zero[0]" stuck at VCC
Info: Implemented 172 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 24 output pins
    Info: Implemented 145 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Processing ended: Mon Jan 14 08:05:21 2002
    Info: Elapsed time: 00:00:07