ram.v

来自「夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） model」· Verilog 代码 · 共 21 行

module ram(data,addr,ena,read,write);
 inout[7:0] data;
 input[9:0] addr;
 input ena;
 input read,write;
 reg[7:0] ram[1023:0];
 
 assign data=(read&&ena)? ram[addr]:8'hzz;
 
/* always @(read or ena or addr)
    if(read&&ena)
      data<=mem[addr];
    else
      data<=8'hzz;  */
   
 always @(posedge write)
  begin
   ram[addr]<=data;
  end
endmodule