risc_cpu.cr.mti

来自「夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） model」· MTI 代码 · 共 122 行

D:/modelsim/RISC_CPU/counter.v {1 {vlog -work work -novopt -nocovercells D:/modelsim/RISC_CPU/counter.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module counter

Top level modules:
	counter

} {} {}} D:/modelsim/RISC_CPU/machinectl.v {1 {vlog -work work -novopt -nocovercells D:/modelsim/RISC_CPU/machinectl.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module machinectl

Top level modules:
	machinectl

} {} {}} D:/modelsim/RISC_CPU/alu.v {1 {vlog -work work -novopt -nocovercells D:/modelsim/RISC_CPU/alu.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module alu

Top level modules:
	alu

} {} {}} D:/modelsim/RISC_CPU/clk_gen.v {1 {vlog -work work -novopt -nocovercells D:/modelsim/RISC_CPU/clk_gen.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module clk_gen

Top level modules:
	clk_gen

} {} {}} D:/modelsim/RISC_CPU/register.v {1 {vlog -work work -novopt -nocovercells D:/modelsim/RISC_CPU/register.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module register

Top level modules:
	register

} {} {}} D:/modelsim/RISC_CPU/addr_decode.v {1 {vlog -work work -novopt -nocovercells D:/modelsim/RISC_CPU/addr_decode.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module addr_decode

Top level modules:
	addr_decode

} {} {}} D:/modelsim/RISC_CPU/rom.v {1 {vlog -work work -novopt -nocovercells D:/modelsim/RISC_CPU/rom.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module rom

Top level modules:
	rom

} {} {}} D:/modelsim/RISC_CPU/adr.v {1 {vlog -work work -novopt -nocovercells D:/modelsim/RISC_CPU/adr.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module adr

Top level modules:
	adr

} {} {}} D:/modelsim/RISC_CPU/ram.v {1 {vlog -work work -novopt -nocovercells D:/modelsim/RISC_CPU/ram.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module ram

Top level modules:
	ram

} {} {}} D:/modelsim/RISC_CPU/cpu.v {1 {vlog -work work -novopt -nocovercells D:/modelsim/RISC_CPU/cpu.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module register
-- Compiling module accum
-- Compiling module alu
-- Compiling module datactl
-- Compiling module adr
-- Compiling module counter
-- Compiling module machinectl
-- Compiling module machine
-- Compiling module clk_gen
-- Compiling module cpu

Top level modules:
	cpu

} {} {}} D:/modelsim/RISC_CPU/accum.v {1 {vlog -work work -novopt -nocovercells D:/modelsim/RISC_CPU/accum.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module accum

Top level modules:
	accum

} {} {}} D:/modelsim/RISC_CPU/cputop.v {1 {vlog -work work -novopt -nocovercells D:/modelsim/RISC_CPU/cputop.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module ram
-- Compiling module rom
-- Compiling module addr_decode
-- Compiling module register
-- Compiling module accum
-- Compiling module alu
-- Compiling module datactl
-- Compiling module adr
-- Compiling module counter
-- Compiling module machinectl
-- Compiling module machine
-- Compiling module clk_gen
-- Compiling module cpu
-- Compiling module cputop

Top level modules:
	cputop

} {} {}} D:/modelsim/RISC_CPU/datactl.v {1 {vlog -work work -novopt -nocovercells D:/modelsim/RISC_CPU/datactl.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module datactl

Top level modules:
	datactl

} {} {}} D:/modelsim/RISC_CPU/machine.v {1 {vlog -work work -novopt -nocovercells D:/modelsim/RISC_CPU/machine.v
Model Technology ModelSim SE vlog 6.4 Compiler 2008.06 Jun 18 2008
-- Compiling module machine

Top level modules:
	machine

} {} {}}