serial.v

鼠标的verilog驱动

module serial(
					input	wire[7:0]	data_in,
					input	wire		Txd_star,
					input	wire		reset,
					input	wire		clk,
					output	reg			data_out,
					output	reg[3:0]	s_state
					);
reg	[20:0]	acc=0;
//reg	[3:0]	s_state;
reg [1:0] pose_Baud;
reg	[7:0]	SBUF;
wire		BaudTick;
assign	BaudTick	=	(pose_Baud == 2'b01);

always@(posedge	clk	or	negedge	reset)
begin
	if(reset	==	0)
	SBUF[7:0]	<=	8'b00000000;
	else if(Txd_star	==	1)
	SBUF[7:0]	<=	data_in[7:0];
	else
	SBUF	<=	SBUF;
end

always@(	posedge	clk	or	negedge	reset)
begin
	if(reset	==	0)
		acc	<=	0;
	else
	acc	<=	acc	+201;
end

always@(posedge clk or negedge reset)
begin
    if(reset ==0 )
       pose_Baud <= 2'b0;
    else
       pose_Baud[1:0] <= {pose_Baud[0],acc[20]};
end

always@(posedge	clk	or	negedge	reset)
begin
	if(reset	==	0)
		s_state	<=	4'b1111;
	else
		case(	s_state	)
		   4'b1111:	if(Txd_star	==	1)	s_state	<=	4'b0000;
			4'b0000:	if(BaudTick	==	1)	s_state	<=	4'b0001;
			4'b0001:	if(BaudTick	==	1)	s_state	<=	4'b0010;
			4'b0010:	if(BaudTick	==	1)	s_state	<=	4'b0011;
			4'b0011:	if(BaudTick	==	1)	s_state	<=	4'b0100;
			4'b0100:	if(BaudTick	==	1)	s_state	<=	4'b0101;
			4'b0101:	if(BaudTick	==	1)	s_state	<=	4'b0110;
			4'b0110:	if(BaudTick	==	1)	s_state	<=	4'b0111;
			4'b0111:	if(BaudTick	==	1)	s_state	<=	4'b1000;
			4'b1000:	if(BaudTick	==	1)	s_state	<=	4'b1001;
			4'b1001:	if(BaudTick	==	1)	s_state	<=	4'b1010;
			4'b1010:	if(BaudTick	==	1)	s_state	<=	4'b1111;
			default	s_state	<=	4'b1111;
		endcase
end

always@(s_state)
begin
	case(	s_state	)
	4'b0001:	data_out	<=	1'b0;
	4'b0010:	data_out	<=	SBUF[0];
	4'b0011:	data_out	<=	SBUF[1];
	4'b0100:	data_out	<= SBUF[2];
	4'b0101:	data_out	<= SBUF[3];
	4'b0110:	data_out	<=	SBUF[4];
	4'b0111:	data_out	<=	SBUF[5];
	4'b1000:	data_out	<=	SBUF[6];
	4'b1001:	data_out	<=	SBUF[7];
	4'b0000:	data_out	<=	1'b1;
	default		data_out	<=	1'b1;
	endcase
end

endmodule