ps2_serial_top.v

鼠标的verilog驱动

module ps2_serial_top(
						input	wire	reset,
						input	wire	clk,
						inout			ps2_data,
						inout			ps2_clk,
						output	wire	data_out,
						output	wire	lfbut,
						output	wire	rgbut
					);
wire[7:0]	xcont;
wire[7:0]	ycont;
wire		data_rdy;
wire		Txd_star;
wire[7:0]	data_send;
wire[3:0]	s_state;

ps2_mouse_ctr	myps2(.reset(reset),.clk(clk),.ps2_data_mouse(ps2_data),.ps2_clk_mouse(ps2_clk),
				.xcont(xcont),.ycont(ycont),.lfbut(lfbut),.rgbut(rgbut),.all_data_rdy(data_rdy));
ps2_link_serial	mylink(.data_in_x(xcont),.data_in_y(ycont),.data_rdy(data_rdy),.reset(reset),
				.clk(clk),.Txd_star(Txd_star),.data_send(data_send),.s_state(s_state));
serial	myserial(.clk(clk),.reset(reset),.data_in(data_send),.Txd_star(Txd_star),
				.data_out(data_out),.s_state(s_state));
endmodule










module ps2_link_serial(
						input	wire[7:0]	data_in_x,
						input	wire[7:0]	data_in_y,
						input	wire[3:0]	s_state,
						input	wire		data_rdy,
						input	wire		reset,
						input	wire		clk,
						output	reg			Txd_star,
						output	reg[7:0]	data_send
						);

reg[1:0]	state_s;
reg[2:0]	data_rdy_buf;

always@(posedge	clk	or	negedge	reset)
begin
	if(reset	==	0)
	data_rdy_buf	<=	3'b000;
	else
	data_rdy_buf[2:0]	<=	{data_rdy_buf[1:0],data_rdy};
end

always@(posedge	clk	or	negedge	reset)
begin
	if(reset	==	0)
	begin
		Txd_star	<=	1'b0;
		state_s		<=	2'b00;
	end
	else if(data_rdy_buf==	3'b100)
	begin
		//data_send	<=	8'd9;
		Txd_star	<=	1'b1;
		state_s	<=	2'b01;
	end
	else if((state_s==2'b01)&&(s_state==4'b1111))
	begin
		data_send	<=	data_in_x;
		Txd_star	<=	1'b1;
		state_s	<=	2'b11;
	end
	else if((state_s==2'b11)&&(s_state==4'b1111))
	begin
		data_send	<=	data_in_y;
		Txd_star	<=	1'b1;
		state_s	<=	2'b00;
	end
	else
	begin
		data_send	<=	data_send;
		Txd_star	<=	1'b0;
		state_s	<=	state_s;
	end
end
endmodule