atmega16.tan.qmsg

基于FPGA的DDS正弦信号发生器,信号失真小

{ "Info" "ITDB_TSU_RESULT" "dds:inst\|dds_m\[5\] key\[0\] clk -0.293 ns register " "Info: tsu for register \"dds:inst\|dds_m\[5\]\" (data pin = \"key\[0\]\", clock pin = \"clk\") is -0.293 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.497 ns + Longest pin register " "Info: + Longest pin to register delay is 11.497 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns key\[0\] 1 PIN PIN_53 26 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_53; Fanout = 26; PIN Node = 'key\[0\]'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { key[0] } "NODE_NAME" } } { "../通信3（干活）/atmega16.bdf" "" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 96 -32 136 112 "key\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.911 ns) + CELL(0.978 ns) 7.021 ns dds:inst\|Add3~660 2 COMB LC_X4_Y3_N1 2 " "Info: 2: + IC(4.911 ns) + CELL(0.978 ns) = 7.021 ns; Loc. = LC_X4_Y3_N1; Fanout = 2; COMB Node = 'dds:inst\|Add3~660'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.889 ns" { key[0] dds:inst|Add3~660 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 151 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 7.144 ns dds:inst\|Add3~654 3 COMB LC_X4_Y3_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.123 ns) = 7.144 ns; Loc. = LC_X4_Y3_N2; Fanout = 2; COMB Node = 'dds:inst\|Add3~654'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { dds:inst|Add3~660 dds:inst|Add3~654 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 151 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.123 ns) 7.267 ns dds:inst\|Add3~648 4 COMB LC_X4_Y3_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.123 ns) = 7.267 ns; Loc. = LC_X4_Y3_N3; Fanout = 2; COMB Node = 'dds:inst\|Add3~648'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.123 ns" { dds:inst|Add3~654 dds:inst|Add3~648 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 151 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.261 ns) 7.528 ns dds:inst\|Add3~666 5 COMB LC_X4_Y3_N4 5 " "Info: 5: + IC(0.000 ns) + CELL(0.261 ns) = 7.528 ns; Loc. = LC_X4_Y3_N4; Fanout = 5; COMB Node = 'dds:inst\|Add3~666'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.261 ns" { dds:inst|Add3~648 dds:inst|Add3~666 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 151 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.975 ns) 8.503 ns dds:inst\|Add3~656 6 COMB LC_X4_Y3_N5 1 " "Info: 6: + IC(0.000 ns) + CELL(0.975 ns) = 8.503 ns; Loc. = LC_X4_Y3_N5; Fanout = 1; COMB Node = 'dds:inst\|Add3~656'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.975 ns" { dds:inst|Add3~666 dds:inst|Add3~656 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 151 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.403 ns) + CELL(0.591 ns) 11.497 ns dds:inst\|dds_m\[5\] 7 REG LC_X3_Y2_N5 8 " "Info: 7: + IC(2.403 ns) + CELL(0.591 ns) = 11.497 ns; Loc. = LC_X3_Y2_N5; Fanout = 8; REG Node = 'dds:inst\|dds_m\[5\]'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.994 ns" { dds:inst|Add3~656 dds:inst|dds_m[5] } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 144 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.183 ns ( 36.38 % ) " "Info: Total cell delay = 4.183 ns ( 36.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.314 ns ( 63.62 % ) " "Info: Total interconnect delay = 7.314 ns ( 63.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "11.497 ns" { key[0] dds:inst|Add3~660 dds:inst|Add3~654 dds:inst|Add3~648 dds:inst|Add3~666 dds:inst|Add3~656 dds:inst|dds_m[5] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "11.497 ns" { key[0] key[0]~combout dds:inst|Add3~660 dds:inst|Add3~654 dds:inst|Add3~648 dds:inst|Add3~666 dds:inst|Add3~656 dds:inst|dds_m[5] } { 0.000ns 0.000ns 4.911ns 0.000ns 0.000ns 0.000ns 0.000ns 2.403ns } { 0.000ns 1.132ns 0.978ns 0.123ns 0.123ns 0.261ns 0.975ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 144 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.123 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 12.123 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../通信3（干活）/atmega16.bdf" "" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 80 -32 136 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns dds:inst\|cp_65k 2 REG LC_X2_Y3_N4 25 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N4; Fanout = 25; REG Node = 'dds:inst\|cp_65k'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk dds:inst|cp_65k } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(1.294 ns) 7.764 ns dds:inst\|cp_1k 3 REG LC_X2_Y2_N0 12 " "Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.764 ns; Loc. = LC_X2_Y2_N0; Fanout = 12; REG Node = 'dds:inst\|cp_1k'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.040 ns" { dds:inst|cp_65k dds:inst|cp_1k } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.441 ns) + CELL(0.918 ns) 12.123 ns dds:inst\|dds_m\[5\] 4 REG LC_X3_Y2_N5 8 " "Info: 4: + IC(3.441 ns) + CELL(0.918 ns) = 12.123 ns; Loc. = LC_X3_Y2_N5; Fanout = 8; REG Node = 'dds:inst\|dds_m\[5\]'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.359 ns" { dds:inst|cp_1k dds:inst|dds_m[5] } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 144 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 38.51 % ) " "Info: Total cell delay = 4.669 ns ( 38.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.454 ns ( 61.49 % ) " "Info: Total interconnect delay = 7.454 ns ( 61.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "12.123 ns" { clk dds:inst|cp_65k dds:inst|cp_1k dds:inst|dds_m[5] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "12.123 ns" { clk clk~combout dds:inst|cp_65k dds:inst|cp_1k dds:inst|dds_m[5] } { 0.000ns 0.000ns 1.267ns 2.746ns 3.441ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "11.497 ns" { key[0] dds:inst|Add3~660 dds:inst|Add3~654 dds:inst|Add3~648 dds:inst|Add3~666 dds:inst|Add3~656 dds:inst|dds_m[5] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "11.497 ns" { key[0] key[0]~combout dds:inst|Add3~660 dds:inst|Add3~654 dds:inst|Add3~648 dds:inst|Add3~666 dds:inst|Add3~656 dds:inst|dds_m[5] } { 0.000ns 0.000ns 4.911ns 0.000ns 0.000ns 0.000ns 0.000ns 2.403ns } { 0.000ns 1.132ns 0.978ns 0.123ns 0.123ns 0.261ns 0.975ns 0.591ns } "" } } { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "12.123 ns" { clk dds:inst|cp_65k dds:inst|cp_1k dds:inst|dds_m[5] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "12.123 ns" { clk clk~combout dds:inst|cp_65k dds:inst|cp_1k dds:inst|dds_m[5] } { 0.000ns 0.000ns 1.267ns 2.746ns 3.441ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk datap\[0\] dds:inst\|dds_add\[12\] 20.992 ns register " "Info: tco from clock \"clk\" to destination pin \"datap\[0\]\" through register \"dds:inst\|dds_add\[12\]\" is 20.992 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.388 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.388 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../通信3（干活）/atmega16.bdf" "" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 80 -32 136 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns dds:inst\|cp_65k 2 REG LC_X2_Y3_N4 25 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N4; Fanout = 25; REG Node = 'dds:inst\|cp_65k'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk dds:inst|cp_65k } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(0.918 ns) 7.388 ns dds:inst\|dds_add\[12\] 3 REG LC_X6_Y2_N4 34 " "Info: 3: + IC(2.746 ns) + CELL(0.918 ns) = 7.388 ns; Loc. = LC_X6_Y2_N4; Fanout = 34; REG Node = 'dds:inst\|dds_add\[12\]'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.664 ns" { dds:inst|cp_65k dds:inst|dds_add[12] } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 45.68 % ) " "Info: Total cell delay = 3.375 ns ( 45.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.013 ns ( 54.32 % ) " "Info: Total interconnect delay = 4.013 ns ( 54.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.388 ns" { clk dds:inst|cp_65k dds:inst|dds_add[12] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "7.388 ns" { clk clk~combout dds:inst|cp_65k dds:inst|dds_add[12] } { 0.000ns 0.000ns 1.267ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 131 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.228 ns + Longest register pin " "Info: + Longest register to pin delay is 13.228 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dds:inst\|dds_add\[12\] 1 REG LC_X6_Y2_N4 34 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X6_Y2_N4; Fanout = 34; REG Node = 'dds:inst\|dds_add\[12\]'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { dds:inst|dds_add[12] } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 131 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.941 ns) + CELL(0.914 ns) 1.855 ns dds:inst\|Mux26~358 2 COMB LC_X6_Y2_N8 4 " "Info: 2: + IC(0.941 ns) + CELL(0.914 ns) = 1.855 ns; Loc. = LC_X6_Y2_N8; Fanout = 4; COMB Node = 'dds:inst\|Mux26~358'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.855 ns" { dds:inst|dds_add[12] dds:inst|Mux26~358 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.876 ns) + CELL(0.740 ns) 4.471 ns dds:inst\|Mux26~362 3 COMB LC_X6_Y1_N0 2 " "Info: 3: + IC(1.876 ns) + CELL(0.740 ns) = 4.471 ns; Loc. = LC_X6_Y1_N0; Fanout = 2; COMB Node = 'dds:inst\|Mux26~362'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.616 ns" { dds:inst|Mux26~358 dds:inst|Mux26~362 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.838 ns) + CELL(0.511 ns) 6.820 ns dds:inst\|Mux26~363 4 COMB LC_X7_Y2_N1 1 " "Info: 4: + IC(1.838 ns) + CELL(0.511 ns) = 6.820 ns; Loc. = LC_X7_Y2_N1; Fanout = 1; COMB Node = 'dds:inst\|Mux26~363'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { dds:inst|Mux26~362 dds:inst|Mux26~363 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.852 ns) + CELL(0.511 ns) 9.183 ns dds:inst\|Mux26~365 5 COMB LC_X6_Y1_N2 1 " "Info: 5: + IC(1.852 ns) + CELL(0.511 ns) = 9.183 ns; Loc. = LC_X6_Y1_N2; Fanout = 1; COMB Node = 'dds:inst\|Mux26~365'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.363 ns" { dds:inst|Mux26~363 dds:inst|Mux26~365 } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 170 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.723 ns) + CELL(2.322 ns) 13.228 ns datap\[0\] 6 PIN PIN_40 0 " "Info: 6: + IC(1.723 ns) + CELL(2.322 ns) = 13.228 ns; Loc. = PIN_40; Fanout = 0; PIN Node = 'datap\[0\]'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.045 ns" { dds:inst|Mux26~365 datap[0] } "NODE_NAME" } } { "../通信3（干活）/atmega16.bdf" "" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 80 376 552 96 "datap\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.998 ns ( 37.78 % ) " "Info: Total cell delay = 4.998 ns ( 37.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.230 ns ( 62.22 % ) " "Info: Total interconnect delay = 8.230 ns ( 62.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "13.228 ns" { dds:inst|dds_add[12] dds:inst|Mux26~358 dds:inst|Mux26~362 dds:inst|Mux26~363 dds:inst|Mux26~365 datap[0] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "13.228 ns" { dds:inst|dds_add[12] dds:inst|Mux26~358 dds:inst|Mux26~362 dds:inst|Mux26~363 dds:inst|Mux26~365 datap[0] } { 0.000ns 0.941ns 1.876ns 1.838ns 1.852ns 1.723ns } { 0.000ns 0.914ns 0.740ns 0.511ns 0.511ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.388 ns" { clk dds:inst|cp_65k dds:inst|dds_add[12] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "7.388 ns" { clk clk~combout dds:inst|cp_65k dds:inst|dds_add[12] } { 0.000ns 0.000ns 1.267ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "13.228 ns" { dds:inst|dds_add[12] dds:inst|Mux26~358 dds:inst|Mux26~362 dds:inst|Mux26~363 dds:inst|Mux26~365 datap[0] } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "13.228 ns" { dds:inst|dds_add[12] dds:inst|Mux26~358 dds:inst|Mux26~362 dds:inst|Mux26~363 dds:inst|Mux26~365 datap[0] } { 0.000ns 0.941ns 1.876ns 1.838ns 1.852ns 1.723ns } { 0.000ns 0.914ns 0.740ns 0.511ns 0.511ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "dds:inst\|bell key\[1\] clk 5.705 ns register " "Info: th for register \"dds:inst\|bell\" (data pin = \"key\[1\]\", clock pin = \"clk\") is 5.705 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.123 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 12.123 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 25 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 25; CLK Node = 'clk'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "../通信3（干活）/atmega16.bdf" "" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 80 -32 136 96 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns dds:inst\|cp_65k 2 REG LC_X2_Y3_N4 25 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N4; Fanout = 25; REG Node = 'dds:inst\|cp_65k'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk dds:inst|cp_65k } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 80 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(1.294 ns) 7.764 ns dds:inst\|cp_1k 3 REG LC_X2_Y2_N0 12 " "Info: 3: + IC(2.746 ns) + CELL(1.294 ns) = 7.764 ns; Loc. = LC_X2_Y2_N0; Fanout = 12; REG Node = 'dds:inst\|cp_1k'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.040 ns" { dds:inst|cp_65k dds:inst|cp_1k } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.441 ns) + CELL(0.918 ns) 12.123 ns dds:inst\|bell 4 REG LC_X3_Y2_N6 1 " "Info: 4: + IC(3.441 ns) + CELL(0.918 ns) = 12.123 ns; Loc. = LC_X3_Y2_N6; Fanout = 1; REG Node = 'dds:inst\|bell'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.359 ns" { dds:inst|cp_1k dds:inst|bell } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns ( 38.51 % ) " "Info: Total cell delay = 4.669 ns ( 38.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.454 ns ( 61.49 % ) " "Info: Total interconnect delay = 7.454 ns ( 61.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "12.123 ns" { clk dds:inst|cp_65k dds:inst|cp_1k dds:inst|bell } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "12.123 ns" { clk clk~combout dds:inst|cp_65k dds:inst|cp_1k dds:inst|bell } { 0.000ns 0.000ns 1.267ns 2.746ns 3.441ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 73 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.639 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.639 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns key\[1\] 1 PIN PIN_52 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_52; Fanout = 2; PIN Node = 'key\[1\]'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { key[1] } "NODE_NAME" } } { "../通信3（干活）/atmega16.bdf" "" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 96 -32 136 112 "key\[1..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.703 ns) + CELL(0.804 ns) 6.639 ns dds:inst\|bell 2 REG LC_X3_Y2_N6 1 " "Info: 2: + IC(4.703 ns) + CELL(0.804 ns) = 6.639 ns; Loc. = LC_X3_Y2_N6; Fanout = 1; REG Node = 'dds:inst\|bell'" {  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.507 ns" { key[1] dds:inst|bell } "NODE_NAME" } } { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 73 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.936 ns ( 29.16 % ) " "Info: Total cell delay = 1.936 ns ( 29.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.703 ns ( 70.84 % ) " "Info: Total interconnect delay = 4.703 ns ( 70.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.639 ns" { key[1] dds:inst|bell } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "6.639 ns" { key[1] key[1]~combout dds:inst|bell } { 0.000ns 0.000ns 4.703ns } { 0.000ns 1.132ns 0.804ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "12.123 ns" { clk dds:inst|cp_65k dds:inst|cp_1k dds:inst|bell } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "12.123 ns" { clk clk~combout dds:inst|cp_65k dds:inst|cp_1k dds:inst|bell } { 0.000ns 0.000ns 1.267ns 2.746ns 3.441ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } "" } } { "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "6.639 ns" { key[1] dds:inst|bell } "NODE_NAME" } } { "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/quartus2/quartus/bin/Technology_Viewer.qrui" "6.639 ns" { key[1] key[1]~combout dds:inst|bell } { 0.000ns 0.000ns 4.703ns } { 0.000ns 1.132ns 0.804ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "105 " "Info: Allocated 105 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 06 13:02:24 2008 " "Info: Processing ended: Thu Nov 06 13:02:24 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}