atmega16.map.qmsg

基于FPGA的DDS正弦信号发生器,信号失真小

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.0 Build 33 02/05/2007 SJ Full Version " "Info: Version 7.0 Build 33 02/05/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 06 13:02:03 2008 " "Info: Processing started: Thu Nov 06 13:02:03 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off atmega16 -c atmega16 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off atmega16 -c atmega16" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../通信3（干活）/atmega16.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../通信3（干活）/atmega16.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 atmega16 " "Info: Found entity 1: atmega16" {  } { { "../通信3（干活）/atmega16.bdf" "" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../通信3（干活）/atmeg16.vhd 4 2 " "Info: Found 4 design units, including 2 entities, in source file ../通信3（干活）/atmeg16.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 tx3-wzy " "Info: Found design unit 1: tx3-wzy" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 14 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 dds-dac " "Info: Found design unit 2: dds-dac" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 79 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 tx3 " "Info: Found entity 1: tx3" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 dds " "Info: Found entity 2: dds" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 68 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "atmega16 " "Info: Elaborating entity \"atmega16\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "tx3 inst1 " "Warning: Block or symbol \"tx3\" of instance \"inst1\" overlaps another block or symbol" {  } { { "../通信3（干活）/atmega16.bdf" "" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 104 496 672 200 "inst1" "" } } } }  } 0 0 "Block or symbol \"%1!s!\" of instance \"%2!s!\" overlaps another block or symbol" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dds dds:inst " "Info: Elaborating entity \"dds\" for hierarchy \"dds:inst\"" {  } { { "../通信3（干活）/atmega16.bdf" "inst" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 56 168 336 184 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tx3 tx3:inst1 " "Info: Elaborating entity \"tx3\" for hierarchy \"tx3:inst1\"" {  } { { "../通信3（干活）/atmega16.bdf" "inst1" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 104 496 672 200 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data atmeg16.vhd(55) " "Warning (10492): VHDL Process Statement warning at atmeg16.vhd(55): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 55 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data atmeg16.vhd(56) " "Warning (10492): VHDL Process Statement warning at atmeg16.vhd(56): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 56 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data atmeg16.vhd(57) " "Warning (10492): VHDL Process Statement warning at atmeg16.vhd(57): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 57 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "data atmeg16.vhd(58) " "Warning (10492): VHDL Process Statement warning at atmeg16.vhd(58): signal \"data\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "../通信3（干活）/atmeg16.vhd" "" { Text "F:/王振宇/CPLD/我的程序/通信3（干活）/atmeg16.vhd" 58 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "cs GND " "Warning: Pin \"cs\" stuck at GND" {  } { { "../通信3（干活）/atmega16.bdf" "" { Schematic "F:/王振宇/CPLD/我的程序/通信3（干活）/atmega16.bdf" { { 96 376 552 112 "cs" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "205 " "Info: Implemented 205 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "17 " "Info: Implemented 17 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "185 " "Info: Implemented 185 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 06 13:02:09 2008 " "Info: Processing ended: Thu Nov 06 13:02:09 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}