📄 atmeg16.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity tx3 is
port(clk:in std_logic;
indata: in std_logic_vector(15 downto 0);
outdata:out std_logic_vector(3 downto 0);
address:out std_logic_vector(1 downto 0)
);
end tx3;
ARCHITECTURE wzy OF tx3 IS
--SIGNAL counter: integer range 65536 to 0;
--type state_type is (song0,song1,song2,song3);
--signal present_state,next_state:state_type;
signal clock: std_logic;
signal data: std_logic_vector(15 downto 0);
signal add : std_logic_vector(1 downto 0);
begin
data<=indata;
-------------------------------------------------------------------------------------------------------------
process(clk)--分频进程(2000HZ)
variable cnt1 : integer range 0 to 50;
variable cnt2 : integer range 0 to 50;
begin
if clk'event and clk='1' then
if cnt1=50 then
cnt1:=0;
if cnt2=50 then
cnt2:=0;
clock<=not clock;
else
cnt2:=cnt2+1;
end if;
else
cnt1:=cnt1+1;
end if;
end if;
end process;
------------------------------------------------------------------------------------------------
------------------------------------------------------------------------------------
process(clock) --地址累加
begin
if rising_edge(clock) then
add<=add+1;
end if;
end process;
-------------------------------------------------------------------------------------------------
process(add) --发送进程
begin
case add is
when "00" => outdata<=data(3 downto 0) ;address<=add;
when "01" => outdata<=data(7 downto 4) ;address<=add;
when "10" => outdata<=data(11 downto 8) ;address<=add;
when "11" => outdata<=data(15 downto 12) ;address<=add;
end case;
end process;
end wzy;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dds IS
PORT(clk : in std_logic;
key : in std_logic_vector(1 downto 0);
data : out integer RANGE 255 DOWNTO 0;
cs : out std_logic;
bell : out std_logic;
wr : out std_logic;
outdata: out integer RANGE 65535 DOWNTO 0
);
END dds;
--******************构造体定义*********************
ARCHITECTURE dac OF dds IS
signal cp_65k :std_logic;--65kHz时钟
signal cp_wr :std_logic;--ad时钟
signal cp_1k :std_logic;--1kHz时钟
signal p : integer range 0 to 255;
signal dds_add:integer range 65535 downto 0 :=0;--DDS地址累加器
signal da_dat:integer range 255 downto 0 :=255;--DA缓冲输出
signal dds_m : integer range 1 to 1000 ;--dds频率寄存器
BEGIN
cs<='0';
wr<=cp_wr;
data<=da_dat ;--WHEN cp_wr='0'; --消隐LED点阵
--ELSE 255;
outdata<=dds_m;
--*********************65536Hz分频进程************************
process(clk)
variable cnt1 : integer range 0 to 762;
begin
if clk'event and clk='1' then
case cnt1 IS
WHEN 381 =>
cp_65k<='1';
cnt1:=cnt1+1;
WHEN 762=>
cnt1:=0;
cp_65k<='0';
cp_wr<='0';
WHEN 20=>
cp_wr<='1';
cnt1:=cnt1+1;
WHEN OTHERS=>
cnt1:=cnt1+1;
end case;
end if;
end process;
--*********************1kHz分频进程************************
process(cp_65k)
variable cnt1 : integer range 0 to 64;
begin
if cp_65k'event and cp_65k='1' then
case cnt1 is
when 32=>cp_1k<='1';
cnt1:=cnt1+1;
when 64=>cnt1:=0;
cp_1k<='0';
when others=>cnt1:=cnt1+1;
end case;
end if;
end process;
--**************DDS地址累加器进程**********************
PROCESS(cp_65k)
BEGIN
IF(cp_65k'EVENT AND cp_65k='1') THEN
--DDS累加器循环累加dds_m
IF dds_add<65535 THEN
dds_add<=dds_add+dds_m;
ELSE
dds_add<=dds_add+dds_m-65536;
END IF;
END IF;
END PROCESS;
--***********************频率加减控制进程***************************
process(cp_1k)
begin
if cp_1k='1' then
case key is
when "10"=>
wait until key<="00";
bell<='1'; --频率加
if dds_m=1000 then
dds_m<=1;
else
dds_m<=dds_m+1;
end if;
when "01"=>
wait until key<="00"; --频率减
bell<='1';
if dds_m=1000 then
dds_m<=1;
else
dds_m<=dds_m-1;
end if;
when others=>bell<='0';
end case;
end if;
end process;
--****************************查表输出进程******************************
process(dds_add)
VARIABLE dds_add_v:STD_LOGIC_VECTOR(6 DOWNTO 0):="0000000";--ROM地址表
begin
dds_add_v:=CONV_STD_LOGIC_VECTOR(dds_add,16)(15 DOWNTO 9);
CASE CONV_INTEGER(dds_add_v(6 DOWNTO 0)) IS --ROM数据表
--**********正弦函数表************
WHEN 0 =>da_dat<=127;
WHEN 1 =>da_dat<=133;
WHEN 2 =>da_dat<=139;
WHEN 3 =>da_dat<=145;
WHEN 4 =>da_dat<=151;
WHEN 5 =>da_dat<=157;
WHEN 6 =>da_dat<=163;
WHEN 7 =>da_dat<=169;
WHEN 8 =>da_dat<=175;
WHEN 9 =>da_dat<=181;
WHEN 10 =>da_dat<=186;
WHEN 11 =>da_dat<=192;
WHEN 12 =>da_dat<=197;
WHEN 13 =>da_dat<=202;
WHEN 14 =>da_dat<=207;
WHEN 15 =>da_dat<=212;
WHEN 16 =>da_dat<=216;
WHEN 17 =>da_dat<=221;
WHEN 18 =>da_dat<=225;
WHEN 19 =>da_dat<=229;
WHEN 20 =>da_dat<=232;
WHEN 21 =>da_dat<=235;
WHEN 22 =>da_dat<=239;
WHEN 23 =>da_dat<=241;
WHEN 24 =>da_dat<=244;
WHEN 25 =>da_dat<=246;
WHEN 26 =>da_dat<=248;
WHEN 27 =>da_dat<=250;
WHEN 28 =>da_dat<=251;
WHEN 29 =>da_dat<=252;
WHEN 30 =>da_dat<=253;
WHEN 31 =>da_dat<=253;
WHEN 32 =>da_dat<=254;
WHEN 33 =>da_dat<=253;
WHEN 34 =>da_dat<=253;
WHEN 35 =>da_dat<=252;
WHEN 36 =>da_dat<=251;
WHEN 37 =>da_dat<=250;
WHEN 38 =>da_dat<=248;
WHEN 39 =>da_dat<=246;
WHEN 40 =>da_dat<=244;
WHEN 41 =>da_dat<=241;
WHEN 42 =>da_dat<=239;
WHEN 43 =>da_dat<=235;
WHEN 44 =>da_dat<=232;
WHEN 45 =>da_dat<=229;
WHEN 46 =>da_dat<=225;
WHEN 47 =>da_dat<=221;
WHEN 48 =>da_dat<=216;
WHEN 49 =>da_dat<=212;
WHEN 50 =>da_dat<=207;
WHEN 51 =>da_dat<=202;
WHEN 52 =>da_dat<=197;
WHEN 53 =>da_dat<=192;
WHEN 54 =>da_dat<=186;
WHEN 55 =>da_dat<=181;
WHEN 56 =>da_dat<=175;
WHEN 57 =>da_dat<=169;
WHEN 58 =>da_dat<=163;
WHEN 59 =>da_dat<=157;
WHEN 60 =>da_dat<=151;
WHEN 61 =>da_dat<=145;
WHEN 62 =>da_dat<=139;
WHEN 63 =>da_dat<=133;
WHEN 64 =>da_dat<=127;
WHEN 65 =>da_dat<=120;
WHEN 66 =>da_dat<=114;
WHEN 67 =>da_dat<=108;
WHEN 68 =>da_dat<=102;
WHEN 69 =>da_dat<=96;
WHEN 70 =>da_dat<=90;
WHEN 71 =>da_dat<=84;
WHEN 72 =>da_dat<=78;
WHEN 73 =>da_dat<=72;
WHEN 74 =>da_dat<=67;
WHEN 75 =>da_dat<=61;
WHEN 76 =>da_dat<=56;
WHEN 77 =>da_dat<=51;
WHEN 78 =>da_dat<=46;
WHEN 79 =>da_dat<=41;
WHEN 80 =>da_dat<=37;
WHEN 81 =>da_dat<=32;
WHEN 82 =>da_dat<=28;
WHEN 83 =>da_dat<=24;
WHEN 84 =>da_dat<=21;
WHEN 85 =>da_dat<=18;
WHEN 86 =>da_dat<=14;
WHEN 87 =>da_dat<=12;
WHEN 88 =>da_dat<=9;
WHEN 89 =>da_dat<=7;
WHEN 90 =>da_dat<=5;
WHEN 91 =>da_dat<=3;
WHEN 92 =>da_dat<=2;
WHEN 93 =>da_dat<=1;
WHEN 94 =>da_dat<=0;
WHEN 95 =>da_dat<=0;
WHEN 96 =>da_dat<=0;
WHEN 97 =>da_dat<=0;
WHEN 98 =>da_dat<=0;
WHEN 99 =>da_dat<=1;
WHEN 100 =>da_dat<=2;
WHEN 101 =>da_dat<=3;
WHEN 102 =>da_dat<=5;
WHEN 103 =>da_dat<=7;
WHEN 104 =>da_dat<=9;
WHEN 105 =>da_dat<=12;
WHEN 106 =>da_dat<=14;
WHEN 107 =>da_dat<=18;
WHEN 108 =>da_dat<=21;
WHEN 109 =>da_dat<=24;
WHEN 110 =>da_dat<=28;
WHEN 111 =>da_dat<=32;
WHEN 112 =>da_dat<=37;
WHEN 113 =>da_dat<=41;
WHEN 114 =>da_dat<=46;
WHEN 115 =>da_dat<=51;
WHEN 116 =>da_dat<=56;
WHEN 117 =>da_dat<=61;
WHEN 118 =>da_dat<=67;
WHEN 119 =>da_dat<=72;
WHEN 120 =>da_dat<=78;
WHEN 121 =>da_dat<=84;
WHEN 122 =>da_dat<=90;
WHEN 123 =>da_dat<=96;
WHEN 124 =>da_dat<=102;
WHEN 125 =>da_dat<=108;
WHEN 126 =>da_dat<=114;
WHEN 127 =>da_dat<=120;
WHEN OTHERS =>da_dat<=127;
end case;
end process;
end dac;
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