or1200_tpram_32x32.v

or1200开源risc cpu的verilog描述实现

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"

module or1200_tpram_32x32(
	// Generic synchronous two-port RAM interface
	clk_a, rst_a, ce_a, we_a, oe_a, addr_a, di_a, do_a,
	clk_b, rst_b, ce_b, we_b, oe_b, addr_b, di_b, do_b
);

//
// Default address and data buses width
//
parameter aw = 5;
parameter dw = 32;

//
// Generic synchronous two-port RAM interface
//
input			clk_a;	// Clock
input			rst_a;	// Reset
input			ce_a;	// Chip enable input
input			we_a;	// Write enable input
input			oe_a;	// Output enable input
input 	[aw-1:0]	addr_a;	// address bus inputs
input	[dw-1:0]	di_a;	// input data bus
output	[dw-1:0]	do_a;	// output data bus
input			clk_b;	// Clock
input			rst_b;	// Reset
input			ce_b;	// Chip enable input
input			we_b;	// Write enable input
input			oe_b;	// Output enable input
input 	[aw-1:0]	addr_b;	// address bus inputs
input	[dw-1:0]	di_b;	// input data bus
output	[dw-1:0]	do_b;	// output data bus

//
// Internal wires and registers
//

reg we_bi;
reg [4:0] addr_bi;
wire [31:0] di_bi=0;
always @(posedge clk_a) begin
    if(rst_a) begin
        we_bi<=1;
        addr_bi<=addr_bi+1;       
    end
    else begin
        we_bi<=0;
        addr_bi<=0;         
    end
end
wire [31:0]data=rst_a?di_bi:di_b;
wire wren=rst_a?we_bi:we_b;
wire [4:0] wraddress=rst_a?addr_bi:addr_b;
dpram32x32 dpram (
	.clock(clk_a),
	.data(data),
	.rdaddress(addr_a),
	.rden(ce_a),
	.wraddress(wraddress),
	.wren(wren),
	.q(do_a));


endmodule