vga_hex_disp.v

该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据

/*
 *  Copyright (C) 2006-2008 CMM Sigma Andrzej Chmielowiec <[e-mail]>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 3
 *  as published by the Free Software Foundation.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  If you want to use this code under other conditions, please contact 
 *  CMM Sigma <[e-mail]>.
 */

/*
 * Module paramters
 * ================
 *
 * DATA_WIDTH - 
 *   Number of bits of data bus for RAM (should be divisible by 4).
 *
 * ADDRESS_WIDTH -
 *   Number of bits of address bus for RAM.
 *
 *
 * Module signals
 * ==============
 *
 * hSync[out] - 
 *   Horizontal synchronization of VGA (D-Sub Connector Pin 13).
 *
 * vSync[out] -
 *   Vertical synchronization of (D-Sub Connector Pin 14).
 *
 * red[out] -
 *   Red color component for given pixel (D-Sub Connector Pin 1).
 *
 * green[out] - 
 *   Green color component for given pixel (D-Sub Connector Pin 2).
 *
 * blue[out] - 
 *   Blue color component for given pixel (D-Sub Connector Pin 3).
 *
 * clk[in] -
 *   Clock signal.
 *
 */
module VgaHexDisp #
(
	parameter DATA_WIDTH = 64,
	parameter ADDRESS_WIDTH = 4
)
(
	output hSync, 
	output vSync, 
	output red, 
	output green, 
	output blue, 
	input clk
);

	wire value;
	wire [11:0] pixel;
	wire [11:0] line;
	
	VgaSync #
	(
		.H_PIXELS(640),
		.V_LINES(480)
	)
	vgaSync
	(
		.hSync(hSync),
		.vSync(vSync),
		.redOut(red),
		.greenOut(green),
		.blueOut(blue),
		.pixel(pixel),
		.line(line),
		.redIn(value),
		.greenIn(value),
		.blueIn(value),
		.clk(clk)
	);

	wire [DATA_WIDTH-1:0] data;
	wire [ADDRESS_WIDTH-1:0] address;

	VgaDispMem #
	(
		.DATA_WIDTH(DATA_WIDTH),
		.ADDRESS_WIDTH(ADDRESS_WIDTH)
	)
	vgaDispMem
	(
		.value(value),
		.pixel(pixel),
		.line(line),
		.data(data),
		.address(address),
		.clk(clk)
	);
	
	RAM #
	(
		.DATA_WIDTH(DATA_WIDTH),
		.ADDRESS_WIDTH(ADDRESS_WIDTH),
		.INIT_FILE("mem_init.mif")
	)
	mem
	(
		.data(data),
		.address(address),
		.we(1'b0),
		.clk(clk)
	);
	
endmodule