vga_disp_mem.v

该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据

/*
 *  Copyright (C) 2006-2008 CMM Sigma Andrzej Chmielowiec <[e-mail]>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 3
 *  as published by the Free Software Foundation.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  If you want to use this code under other conditions, please contact 
 *  CMM Sigma <[e-mail]>.
 */

/*
 * Module parameters
 * =================
 *
 * DATA_WIDTH - 
 *   Number of bits of data bus.
 *
 * ADDRESS_WIDTH -
 *   Number of bits of address bus.
 *
 *
 * Module signals
 * ==============
 * 
 * value[out] - 
 *   Value indicateing if pixel of given coordinates 
 *  (pixel, line) should be displayed 1'b1 or not 1'b0.
 * 
 * pixel[in] -
 *   Number of pixel which is actualy displayed by VGA 
 *   interface.
 *
 * line[in] -
 *   Number of line which is actualy displayed by VGA 
 *   interface.
 *
 * data[in] -
 *   Data bus to the memory which should be displayed.
 *
 * address[out] -
 *   Address to the data which should be displayed.
 *
 * clk[in] -
 *   Clock signal.
 *
 */
module VgaDispMem #
(
	parameter DATA_WIDTH = 4,
	parameter ADDRESS_WIDTH = 4
)
(
	output value,
	input [11:0] pixel,
	input [11:0] line,
	input [DATA_WIDTH-1:0] data,
	output reg [ADDRESS_WIDTH-1:0] address = 1'b0,
	input clk
);

	`define DW (DATA_WIDTH)
	`define AW (ADDRESS_WIDTH)

	reg [`DW-1:0] dataLine = 1'b0;
	reg [7:0] hexEnc;
	
	wire [7:0] hexEncWire;
	
	assign value = hexEnc[7];
	
	/*
	 * This ROM contains graphical representation (8x8 bit 
	 * characters) of all hexadecimal numbers.
	 */
	ROM #
	(
		.DATA_WIDTH(8),
		.ADDRESS_WIDTH(7),
		.INIT_FILE("hex_digit_matrix.mif")
	)
	hexDigitMatrix
	(
		.data(hexEncWire),
		.address({dataLine[`DW-1:`DW-4], line[2:0]}),
		.clk(clk)
	);
	
	always @(posedge clk) begin
	
		if (pixel == 1'b0) begin
			if (line == 3'b111) begin
				address = 1'b0;
			end
			else if (line[2:0] == 3'b111) begin
				address = address + 1'b1;
			end
		end
		else if (pixel == 3'b100) begin
			dataLine = data;
		end
		else if (pixel[2:0] == 3'b100) begin
			dataLine = {dataLine[`DW-5:0], 4'b0};
			hexEnc = {hexEnc[6:0], 1'b0};
		end
		else if (pixel[2:0] == 3'b111 && pixel[11:3] < (`DW / 4) 
			&& 0 < line[11:3] && line[11:3] < ((1 << `AW) + 1)) begin
			hexEnc = hexEncWire;
		end
		else begin
			hexEnc = {hexEnc[6:0], 1'b0};
		end
		
	end

	`undef DW
	`undef AW

endmodule