mem.v

该项目可在VGA显示器上显示ＲＡＭ或ＲＯＭ中的十六进制数据

/*
 *  Copyright (C) 2006-2008 CMM Sigma Andrzej Chmielowiec <[e-mail]>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 3
 *  as published by the Free Software Foundation.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  If you want to use this code under other conditions, please contact 
 *  CMM Sigma <[e-mail]>.
 */

/*
 * Module parameters
 * =================
 *
 * DATA_WIDTH - 
 *   Number of bits of data bus.
 *
 * ADDRESS_WIDTH -
 *   Number of bits of address bus.
 *
 * INIT_FILE -
 *   File with memory initial data.
 *
 * Module signals
 * ==============
 *
 * data[in,out] - 
 *   Data bus to and from the memory.
 *
 * address[in] - 
 *   Address of the data.
 *
 * we[in] - 
 *   Write Enable bit is used to indicate, that write operation 
 *   is expected in the next clock cycle.
 * 
 * clk[in] -
 *   Clock signal.
 *
 */
module RAM #
(
	parameter DATA_WIDTH = 4,
	parameter ADDRESS_WIDTH = 4,
	parameter INIT_FILE = "UNUSED"
)
(
	inout [DATA_WIDTH-1:0] data,
	input [ADDRESS_WIDTH-1:0] address,
	input we,
	input clk
);


	`define DW (DATA_WIDTH)
	`define AW (ADDRESS_WIDTH)
	
	lpm_ram_io #
	(
		.LPM_WIDTH(`DW),
		.LPM_WIDTHAD(`AW),
		.LPM_FILE(INIT_FILE)
	)
	mem
	(
		.dio(data),
		.address(address),
		.we(we),
		.inclock(clk),
		.outclock(clk)
	);

	`undef DW
	`undef AW

endmodule


/*
 * Module parameters
 * =================
 *
 * DATA_WIDTH - 
 *   Number of bits of data bus.
 *
 * ADDRESS_WIDTH -
 *   Number of bits of address bus.
 *
 * INIT_FILE -
 *   File with memory initial data.
 *
 *
 * Module signals
 * ==============
 *
 * data[out] - 
 *   Data bus from the memory.
 *
 * address[in] - 
 *   Address of the data.
 *
 * clk[in] -
 *   Clock signal.
 *
 */
module ROM #
(
	parameter DATA_WIDTH = 4,
	parameter ADDRESS_WIDTH = 4,
	parameter INIT_FILE = "UNUSED"
	
)
(
	output [DATA_WIDTH-1:0] data,
	input [ADDRESS_WIDTH-1:0] address,
	input clk
);

	`define DW (DATA_WIDTH)
	`define AW (ADDRESS_WIDTH)
	
	lpm_rom #
	(
		.LPM_WIDTH(`DW),
		.LPM_WIDTHAD(`AW),
		.LPM_FILE(INIT_FILE)
	)
	mem
	(
		.q(data),
		.address(address),
		.inclock(clk),
		.outclock(clk)
	);

	`undef DW
	`undef AW

endmodule