tenths.edn

一个VHDL编写的时钟的程序

(edif test (edifVersion 2 0 0) (edifLevel 0) (keywordMap (keywordLevel 0))
(status (written (timeStamp 2003 7 8 11 23 16)
   (author "Xilinx, Inc.")
   (program "Xilinx CORE Generator" (version "Xilinx CORE Generator 6.1i"))))
   (comment "                                                                                
      This file is owned and controlled by Xilinx and must be used              
      solely for design, simulation, implementation and creation of             
      design files limited to Xilinx devices or technologies. Use               
      with non-Xilinx devices or technologies is expressly prohibited           
      and immediately terminates your license.                                  
                                                                                
      XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION 'AS IS'             
      SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR                   
      XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION           
      AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION               
      OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS                 
      IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,                   
      AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE          
      FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY                  
      WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE                   
      IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR            
      REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF           
      INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS           
      FOR A PARTICULAR PURPOSE.                                                 
                                                                                
      Xilinx products are not intended for use in life support                  
      appliances, devices, or systems. Use in such applications are             
      expressly prohibited.                                                     
                                                                                
      (c) Copyright 1995-2003 Xilinx, Inc.                                      
      All rights reserved.                                                      
                                                                                
   ")
   (comment "Core parameters: ")
       (comment "c_count_mode = 0 ")
       (comment "c_load_enable = true ")
       (comment "c_has_aset = false ")
       (comment "c_load_low = false ")
       (comment "c_count_to = 1010 ")
       (comment "c_sync_priority = 1 ")
       (comment "c_has_iv = false ")
       (comment "c_restrict_count = true ")
       (comment "c_has_sclr = false ")
       (comment "c_width = 4 ")
       (comment "c_has_q_thresh1 = false ")
       (comment "c_enable_rlocs = true ")
       (comment "c_has_q_thresh0 = true ")
       (comment "c_thresh1_value = 1111111111111111 ")
       (comment "c_has_load = false ")
       (comment "c_thresh_early = true ")
       (comment "c_has_up = false ")
       (comment "c_has_thresh1 = false ")
       (comment "c_has_thresh0 = false ")
       (comment "c_ainit_val = 0001 ")
       (comment "c_has_ce = true ")
       (comment "c_pipe_stages = 0 ")
       (comment "c_family = virtex2 ")
       (comment "InstanceName = tenths ")
       (comment "c_has_aclr = false ")
       (comment "c_sync_enable = 0 ")
       (comment "c_has_ainit = true ")
       (comment "c_sinit_val = 0 ")
       (comment "c_has_sset = false ")
       (comment "c_has_sinit = false ")
       (comment "c_count_by = 0001 ")
       (comment "c_has_l = false ")
       (comment "c_thresh0_value = 1010 ")
   (external xilinxun (edifLevel 0)
      (technology (numberDefinition))
       (cell VCC (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port P (direction OUTPUT))
               )
           )
       )
       (cell GND (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port G (direction OUTPUT))
               )
           )
       )
       (cell FDCE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port CLR (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell FDE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell FDPE (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port D (direction INPUT))
                   (port C (direction INPUT))
                   (port CE (direction INPUT))
                   (port PRE (direction INPUT))
                   (port Q (direction OUTPUT))
               )
           )
       )
       (cell LUT4 (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port I0 (direction INPUT))
                   (port I1 (direction INPUT))
                   (port I2 (direction INPUT))
                   (port I3 (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell MUXCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port DI (direction INPUT))
                   (port CI (direction INPUT))
                   (port S (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
       (cell XORCY (cellType GENERIC)
           (view view_1 (viewType NETLIST)
               (interface
                   (port LI (direction INPUT))
                   (port CI (direction INPUT))
                   (port O (direction OUTPUT))
               )
           )
       )
   )
(library test_lib (edifLevel 0) (technology (numberDefinition (scale 1 (E 1 -12) (unit Time))))
(cell tenths
 (cellType GENERIC) (view view_1 (viewType NETLIST)
  (interface
   (port ( rename CLK "CLK") (direction INPUT))
   (port ( rename CE "CE") (direction INPUT))
   (port ( rename AINIT "AINIT") (direction INPUT))
   (port ( array ( rename Q "Q<3:0>") 4 ) (direction OUTPUT))
   (port ( rename Q_THRESH0 "Q_THRESH0") (direction OUTPUT))
   )
  (contents
   (instance VCC (viewRef view_1 (cellRef VCC  (libraryRef xilinxun))))
   (instance GND (viewRef view_1 (cellRef GND  (libraryRef xilinxun))))
   (instance BU3
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x0y0"))
      (property INIT (string "8888"))
   )
   (instance BU9
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x0y0"))
      (property INIT (string "0020"))
   )
   (instance BU10
      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
      (property RLOC (string "x0y0"))
   )
   (instance BU16
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x0y1"))
      (property INIT (string "0020"))
   )
   (instance BU17
      (viewRef view_1 (cellRef FDE (libraryRef xilinxun)))
      (property RLOC (string "x0y1"))
   )
   (instance BU20
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x0y2"))
      (property INIT (string "eeee"))
   )
   (instance BU22
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x0y2"))
      (property INIT (string "5555"))
   )
   (instance BU23
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "x0y2"))
   )
   (instance BU24
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "x0y2"))
   )
   (instance BU27
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x1y2"))
      (property INIT (string "2222"))
   )
   (instance BU28
      (viewRef view_1 (cellRef FDPE (libraryRef xilinxun)))
      (property RLOC (string "x1y2"))
   )
   (instance BU30
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x0y3"))
      (property INIT (string "aaaa"))
   )
   (instance BU31
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "x0y3"))
   )
   (instance BU32
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "x0y3"))
   )
   (instance BU35
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x1y3"))
      (property INIT (string "2222"))
   )
   (instance BU36
      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
      (property RLOC (string "x1y3"))
   )
   (instance BU38
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x0y3"))
      (property INIT (string "aaaa"))
   )
   (instance BU39
      (viewRef view_1 (cellRef MUXCY (libraryRef xilinxun)))
      (property RLOC (string "x0y3"))
   )
   (instance BU40
      (viewRef view_1 (cellRef XORCY (libraryRef xilinxun)))
      (property RLOC (string "x0y3"))
   )
   (instance BU43
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x1y3"))
      (property INIT (string "2222"))
   )
   (instance BU44
      (viewRef view_1 (cellRef FDCE (libraryRef xilinxun)))
      (property RLOC (string "x1y3"))
   )
   (instance BU46
      (viewRef view_1 (cellRef LUT4 (libraryRef xilinxun)))
      (property RLOC (string "x0y4"))
      (property INIT (string "aaaa"))
   )