bijiaoqi.tan.qmsg

4位电子智能密码锁

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "process0~0 " "Info: Detected gated clock \"process0~0\" as buffer" {  } { { "c:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "process0~0" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "OPEN_LOCK\$latch INA\[2\] ZS 9.700 ns register " "Info: tsu for register \"OPEN_LOCK\$latch\" (data pin = \"INA\[2\]\", clock pin = \"ZS\") is 9.700 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.700 ns + Longest pin register " "Info: + Longest pin to register delay is 11.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.900 ns) 4.900 ns INA\[2\] 1 PIN PIN_23 1 " "Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_23; Fanout = 1; PIN Node = 'INA\[2\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { INA[2] } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.400 ns) + CELL(0.800 ns) 8.100 ns Equal0~34 2 COMB LC2_D16 1 " "Info: 2: + IC(2.400 ns) + CELL(0.800 ns) = 8.100 ns; Loc. = LC2_D16; Fanout = 1; COMB Node = 'Equal0~34'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { INA[2] Equal0~34 } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 9.700 ns Equal0~31 3 COMB LC3_D16 1 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 9.700 ns; Loc. = LC3_D16; Fanout = 1; COMB Node = 'Equal0~31'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { Equal0~34 Equal0~31 } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 11.700 ns OPEN_LOCK\$latch 4 REG LC1_D16 1 " "Info: 4: + IC(0.300 ns) + CELL(1.700 ns) = 11.700 ns; Loc. = LC1_D16; Fanout = 1; REG Node = 'OPEN_LOCK\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { Equal0~31 OPEN_LOCK$latch } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 15 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.000 ns ( 76.92 % ) " "Info: Total cell delay = 9.000 ns ( 76.92 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.700 ns ( 23.08 % ) " "Info: Total interconnect delay = 2.700 ns ( 23.08 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "11.700 ns" { INA[2] Equal0~34 Equal0~31 OPEN_LOCK$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "11.700 ns" { INA[2] INA[2]~out Equal0~34 Equal0~31 OPEN_LOCK$latch } { 0.000ns 0.000ns 2.400ns 0.000ns 0.300ns } { 0.000ns 4.900ns 0.800ns 1.600ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "3.500 ns + " "Info: + Micro setup delay of destination is 3.500 ns" {  } { { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 15 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "ZS destination 5.500 ns - Shortest register " "Info: - Shortest clock path from clock \"ZS\" to destination register is 5.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns ZS 1 CLK PIN_124 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_124; Fanout = 1; CLK Node = 'ZS'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { ZS } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.400 ns) 3.600 ns process0~0 2 COMB LC4_D16 1 " "Info: 2: + IC(0.200 ns) + CELL(1.400 ns) = 3.600 ns; Loc. = LC4_D16; Fanout = 1; COMB Node = 'process0~0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { ZS process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 5.500 ns OPEN_LOCK\$latch 3 REG LC1_D16 1 " "Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 5.500 ns; Loc. = LC1_D16; Fanout = 1; REG Node = 'OPEN_LOCK\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { process0~0 OPEN_LOCK$latch } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 15 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.000 ns ( 90.91 % ) " "Info: Total cell delay = 5.000 ns ( 90.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.500 ns ( 9.09 % ) " "Info: Total interconnect delay = 0.500 ns ( 9.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { ZS process0~0 OPEN_LOCK$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.500 ns" { ZS ZS~out process0~0 OPEN_LOCK$latch } { 0.000ns 0.000ns 0.200ns 0.300ns } { 0.000ns 2.000ns 1.400ns 1.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "11.700 ns" { INA[2] Equal0~34 Equal0~31 OPEN_LOCK$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "11.700 ns" { INA[2] INA[2]~out Equal0~34 Equal0~31 OPEN_LOCK$latch } { 0.000ns 0.000ns 2.400ns 0.000ns 0.300ns } { 0.000ns 4.900ns 0.800ns 1.600ns 1.700ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { ZS process0~0 OPEN_LOCK$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.500 ns" { ZS ZS~out process0~0 OPEN_LOCK$latch } { 0.000ns 0.000ns 0.200ns 0.300ns } { 0.000ns 2.000ns 1.400ns 1.600ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "EN OPEN_LOCK OPEN_LOCK\$latch 13.500 ns register " "Info: tco from clock \"EN\" to destination pin \"OPEN_LOCK\" through register \"OPEN_LOCK\$latch\" is 13.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "EN source 5.700 ns + Longest register " "Info: + Longest clock path from clock \"EN\" to source register is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns EN 1 CLK PIN_126 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 1; CLK Node = 'EN'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.600 ns) 3.800 ns process0~0 2 COMB LC4_D16 1 " "Info: 2: + IC(0.200 ns) + CELL(1.600 ns) = 3.800 ns; Loc. = LC4_D16; Fanout = 1; COMB Node = 'process0~0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { EN process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 5.700 ns OPEN_LOCK\$latch 3 REG LC1_D16 1 " "Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 5.700 ns; Loc. = LC1_D16; Fanout = 1; REG Node = 'OPEN_LOCK\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { process0~0 OPEN_LOCK$latch } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 15 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns ( 91.23 % ) " "Info: Total cell delay = 5.200 ns ( 91.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.500 ns ( 8.77 % ) " "Info: Total interconnect delay = 0.500 ns ( 8.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { EN process0~0 OPEN_LOCK$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.700 ns" { EN EN~out process0~0 OPEN_LOCK$latch } { 0.000ns 0.000ns 0.200ns 0.300ns } { 0.000ns 2.000ns 1.600ns 1.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 15 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.800 ns + Longest register pin " "Info: + Longest register to pin delay is 7.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns OPEN_LOCK\$latch 1 REG LC1_D16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_D16; Fanout = 1; REG Node = 'OPEN_LOCK\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { OPEN_LOCK$latch } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 15 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(6.300 ns) 7.800 ns OPEN_LOCK 2 PIN PIN_92 0 " "Info: 2: + IC(1.500 ns) + CELL(6.300 ns) = 7.800 ns; Loc. = PIN_92; Fanout = 0; PIN Node = 'OPEN_LOCK'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.800 ns" { OPEN_LOCK$latch OPEN_LOCK } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns ( 80.77 % ) " "Info: Total cell delay = 6.300 ns ( 80.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.500 ns ( 19.23 % ) " "Info: Total interconnect delay = 1.500 ns ( 19.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.800 ns" { OPEN_LOCK$latch OPEN_LOCK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.800 ns" { OPEN_LOCK$latch OPEN_LOCK } { 0.000ns 1.500ns } { 0.000ns 6.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { EN process0~0 OPEN_LOCK$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.700 ns" { EN EN~out process0~0 OPEN_LOCK$latch } { 0.000ns 0.000ns 0.200ns 0.300ns } { 0.000ns 2.000ns 1.600ns 1.600ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.800 ns" { OPEN_LOCK$latch OPEN_LOCK } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.800 ns" { OPEN_LOCK$latch OPEN_LOCK } { 0.000ns 1.500ns } { 0.000ns 6.300ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "OPEN_LOCK\$latch INA\[0\] EN -1.100 ns register " "Info: th for register \"OPEN_LOCK\$latch\" (data pin = \"INA\[0\]\", clock pin = \"EN\") is -1.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "EN destination 5.700 ns + Longest register " "Info: + Longest clock path from clock \"EN\" to destination register is 5.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns EN 1 CLK PIN_126 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 1; CLK Node = 'EN'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { EN } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.600 ns) 3.800 ns process0~0 2 COMB LC4_D16 1 " "Info: 2: + IC(0.200 ns) + CELL(1.600 ns) = 3.800 ns; Loc. = LC4_D16; Fanout = 1; COMB Node = 'process0~0'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.800 ns" { EN process0~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.600 ns) 5.700 ns OPEN_LOCK\$latch 3 REG LC1_D16 1 " "Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 5.700 ns; Loc. = LC1_D16; Fanout = 1; REG Node = 'OPEN_LOCK\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { process0~0 OPEN_LOCK$latch } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 15 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.200 ns ( 91.23 % ) " "Info: Total cell delay = 5.200 ns ( 91.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.500 ns ( 8.77 % ) " "Info: Total interconnect delay = 0.500 ns ( 8.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { EN process0~0 OPEN_LOCK$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.700 ns" { EN EN~out process0~0 OPEN_LOCK$latch } { 0.000ns 0.000ns 0.200ns 0.300ns } { 0.000ns 2.000ns 1.600ns 1.600ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 15 0 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.800 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns INA\[0\] 1 PIN PIN_55 1 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 1; PIN Node = 'INA\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { INA[0] } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 3.200 ns Equal0~34 2 COMB LC2_D16 1 " "Info: 2: + IC(0.200 ns) + CELL(1.000 ns) = 3.200 ns; Loc. = LC2_D16; Fanout = 1; COMB Node = 'Equal0~34'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.200 ns" { INA[0] Equal0~34 } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.600 ns) 4.800 ns Equal0~31 3 COMB LC3_D16 1 " "Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 4.800 ns; Loc. = LC3_D16; Fanout = 1; COMB Node = 'Equal0~31'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.600 ns" { Equal0~34 Equal0~31 } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.300 ns) + CELL(1.700 ns) 6.800 ns OPEN_LOCK\$latch 4 REG LC1_D16 1 " "Info: 4: + IC(0.300 ns) + CELL(1.700 ns) = 6.800 ns; Loc. = LC1_D16; Fanout = 1; REG Node = 'OPEN_LOCK\$latch'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.000 ns" { Equal0~31 OPEN_LOCK$latch } "NODE_NAME" } } { "BIJIAOQI.vhd" "" { Text "C:/Documents and Settings/Administrator/桌面/EDA_LOCK_ALL/BIJIAOQI/BIJIAOQI.vhd" 15 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.300 ns ( 92.65 % ) " "Info: Total cell delay = 6.300 ns ( 92.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.500 ns ( 7.35 % ) " "Info: Total interconnect delay = 0.500 ns ( 7.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.800 ns" { INA[0] Equal0~34 Equal0~31 OPEN_LOCK$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.800 ns" { INA[0] INA[0]~out Equal0~34 Equal0~31 OPEN_LOCK$latch } { 0.000ns 0.000ns 0.200ns 0.000ns 0.300ns } { 0.000ns 2.000ns 1.000ns 1.600ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.700 ns" { EN process0~0 OPEN_LOCK$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.700 ns" { EN EN~out process0~0 OPEN_LOCK$latch } { 0.000ns 0.000ns 0.200ns 0.300ns } { 0.000ns 2.000ns 1.600ns 1.600ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "6.800 ns" { INA[0] Equal0~34 Equal0~31 OPEN_LOCK$latch } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "6.800 ns" { INA[0] INA[0]~out Equal0~34 Equal0~31 OPEN_LOCK$latch } { 0.000ns 0.000ns 0.200ns 0.000ns 0.300ns } { 0.000ns 2.000ns 1.000ns 1.600ns 1.700ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "107 " "Info: Allocated 107 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jul 15 20:11:03 2007 " "Info: Processing ended: Sun Jul 15 20:11:03 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}