count_5s.vhd

来自「4位电子智能密码锁」· VHDL 代码 · 共 27 行

--______________________________________________________________
-- COUNT_5S.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT_5S IS
PORT ( CLK : IN STD_LOGIC;
     F5_IN : IN STD_LOGIC;
TIME_OUT : OUT STD_LOGIC );
END;

ARCHITECTURE ONE OF COUNT_5S IS
BEGIN
PROCESS ( CLK)
VARIABLE COUNT : INTEGER RANGE 0 TO 5120;
BEGIN
IF CLK='1' AND CLK'EVENT THEN 
  IF F5_IN='0' THEN COUNT:=0; TIME_OUT<='0';
ELSIF COUNT=5120 THEN TIME_OUT<='1';
  ELSE COUNT:=COUNT+1;
END IF;
--  END IF;
END IF;
END PROCESS;
END;
--______________________________________________________________