📄 bijiaoqi.vhd
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--______________________________________________________________
--BIJIAOQI .VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY BIJIAOQI IS
PORT ( INA, INB : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
RST : IN STD_LOGIC;
EN : IN STD_LOGIC;
ZS : IN STD_LOGIC;
OPEN_LOCK : OUT STD_LOGIC );
END;
ARCHITECTURE ONE OF BIJIAOQI IS
BEGIN
PROCESS ( INA, INB, RST, EN, ZS)
BEGIN
IF RST='1' THEN OPEN_LOCK <='0';
ELSIF EN='1'AND ZS='0'THEN
IF INA=INB THEN OPEN_LOCK <='1';
ELSE OPEN_LOCK <='0';
END IF;
-- END IF;
END IF;
END PROCESS;
END;
--______________________________________________________________
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