count_20s.vhd

来自「4位电子智能密码锁」· VHDL 代码 · 共 30 行

--______________________________________________________________
-- COUNT_20S.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT_20S IS
PORT ( CLK : IN STD_LOGIC;
     BJ_IN : IN STD_LOGIC;
SPEAK : OUT STD_LOGIC ;
ZS_OUT : OUT STD_LOGIC );
END;

ARCHITECTURE ONE OF COUNT_20S IS
BEGIN
PROCESS ( CLK)
VARIABLE COUNT : INTEGER RANGE 0 TO 20480;
VARIABLE SPK : STD_LOGIC;
BEGIN
IF CLK='1' AND CLK'EVENT THEN 
  IF BJ_IN='0' THEN COUNT:=0; SPEAK<='0'; ZS_OUT<='0';
ELSIF COUNT=20480 THEN SPEAK<='0'; SPK:='0';
  ELSE COUNT:=COUNT+1; SPK := NOT SPK; ZS_OUT<='1';
END IF;
--  END IF;
END IF;
SPEAK<= SPK;
END PROCESS;
END;
--______________________________________________________________