first_press.map.rpt

4位电子智能密码锁

; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path          ;
+----------------------------------+-----------------+-----------------+---------------------------------------+
; FIRST_PRESS.vhd                  ; yes             ; User VHDL File  ; E:/zw/EDA/FIRST_PRESS/FIRST_PRESS.vhd ;
+----------------------------------+-----------------+-----------------+---------------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+--------------------------------+------------+
; Resource                       ; Usage      ;
+--------------------------------+------------+
; Total logic elements           ; 9          ;
; Total combinational functions  ; 9          ;
;     -- Total 4-input functions ; 3          ;
;     -- Total 3-input functions ; 5          ;
;     -- Total 2-input functions ; 1          ;
;     -- Total 1-input functions ; 0          ;
;     -- Total 0-input functions ; 0          ;
; Total registers                ; 0          ;
; I/O pins                       ; 7          ;
; Maximum fan-out node           ; RST        ;
; Maximum fan-out                ; 6          ;
; Total fan-out                  ; 31         ;
; Average fan-out                ; 1.94       ;
+--------------------------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                     ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |FIRST_PRESS               ; 9 (9)       ; 0            ; 0           ; 7    ; 9 (9)        ; 0 (0)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |FIRST_PRESS        ;
+----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; TOUT$latch                                         ; KEY_CNT             ; yes                    ;
; KEY_BUFF[0]                                        ; RST                 ; yes                    ;
; KEY_BUFF[1]                                        ; RST                 ; yes                    ;
; KEY_BUFF[2]                                        ; RST                 ; yes                    ;
; KEY_BUFF[3]                                        ; RST                 ; yes                    ;
; KEY_CNT                                            ; comb~0              ; yes                    ;
; Number of user-specified and inferred latches = 6  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 0     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Full Version
    Info: Processing started: Fri Feb 16 09:29:31 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off FIRST_PRESS -c FIRST_PRESS
Info: Found 2 design units, including 1 entities, in source file FIRST_PRESS.vhd
    Info: Found design unit 1: FIRST_PRESS-ONE
    Info: Found entity 1: FIRST_PRESS
Info: Elaborating entity "FIRST_PRESS" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at FIRST_PRESS.vhd(17): signal "RST" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at FIRST_PRESS.vhd(17): signal "KEY_IN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at FIRST_PRESS.vhd(18): signal "KEY_CNT" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at FIRST_PRESS.vhd(19): signal "KEY_BUFF" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10492): VHDL Process Statement warning at FIRST_PRESS.vhd(19): signal "KEY_IN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
Warning (10631): VHDL Process Statement warning at FIRST_PRESS.vhd(15): inferring latch(es) for signal or variable "TOUT", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at FIRST_PRESS.vhd(15): inferring latch(es) for signal or variable "KEY_CNT", which holds its previous value in one or more paths through the process
Warning (10631): VHDL Process Statement warning at FIRST_PRESS.vhd(15): inferring latch(es) for signal or variable "KEY_BUFF", which holds its previous value in one or more paths through the process
Info (10041): Verilog HDL or VHDL info at FIRST_PRESS.vhd(15): inferred latch for "KEY_BUFF[0]"
Info (10041): Verilog HDL or VHDL info at FIRST_PRESS.vhd(15): inferred latch for "KEY_BUFF[1]"
Info (10041): Verilog HDL or VHDL info at FIRST_PRESS.vhd(15): inferred latch for "KEY_BUFF[2]"
Info (10041): Verilog HDL or VHDL info at FIRST_PRESS.vhd(15): inferred latch for "KEY_BUFF[3]"
Info (10041): Verilog HDL or VHDL info at FIRST_PRESS.vhd(15): inferred latch for "KEY_CNT"
Info (10041): Verilog HDL or VHDL info at FIRST_PRESS.vhd(15): inferred latch for "TOUT"
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "CLK"
Info: Implemented 16 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 1 output pins
    Info: Implemented 9 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 10 warnings
    Info: Allocated 131 megabytes of memory during processing
    Info: Processing ended: Fri Feb 16 09:29:34 2007
    Info: Elapsed time: 00:00:03