first_press.vhd

来自「4位电子智能密码锁」· VHDL 代码 · 共 26 行

--______________________________________________________________
-- FIRST_PRESS.VHD
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY FIRST_PRESS IS
PORT ( KEY_IN : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
     CLK, RST : IN STD_LOGIC;
         TOUT : OUT STD_LOGIC );
END;

ARCHITECTURE ONE OF FIRST_PRESS IS
SIGNAL KEY_BUFF : STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL KEY_CNT  : STD_LOGIC;
BEGIN
PROCESS ( CLK )
BEGIN
IF RST='1' THEN TOUT<='0'; KEY_CNT<='0'; KEY_BUFF<= KEY_IN;
  ELSIF KEY_CNT='0' THEN
    IF KEY_BUFF=KEY_IN THEN TOUT<='0';
      ELSE TOUT<='1';KEY_CNT<='1';
    END IF;
END IF;
END PROCESS;
END;
--______________________________________________________________