count_5s.tan.rpt

4位电子智能密码锁

; N/A           ; None        ; 0.700 ns  ; F5_IN ; lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[4]  ; CLK      ;
; N/A           ; None        ; 0.700 ns  ; F5_IN ; lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[3]  ; CLK      ;
; N/A           ; None        ; 0.700 ns  ; F5_IN ; lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[2]  ; CLK      ;
; N/A           ; None        ; 0.700 ns  ; F5_IN ; lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[1]  ; CLK      ;
; N/A           ; None        ; 0.600 ns  ; F5_IN ; lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[12] ; CLK      ;
; N/A           ; None        ; 0.600 ns  ; F5_IN ; lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[10] ; CLK      ;
; N/A           ; None        ; 0.600 ns  ; F5_IN ; lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[9]  ; CLK      ;
; N/A           ; None        ; 0.600 ns  ; F5_IN ; lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[8]  ; CLK      ;
; N/A           ; None        ; 0.600 ns  ; F5_IN ; lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[7]  ; CLK      ;
; N/A           ; None        ; 0.600 ns  ; F5_IN ; lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[6]  ; CLK      ;
; N/A           ; None        ; 0.600 ns  ; F5_IN ; lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[11] ; CLK      ;
+---------------+-------------+-----------+-------+--------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
    Info: Processing started: Sun Jul 15 20:30:29 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off COUNT_5S -c COUNT_5S
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "CLK" is an undefined clock
Info: Clock "CLK" has Internal fmax of 120.48 MHz between source register "lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[5]" and destination register "TIME_OUT~reg0" (period= 8.3 ns)
    Info: + Longest register to register delay is 7.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_B1; Fanout = 3; REG Node = 'lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[5]'
        Info: 2: + IC(0.900 ns) + CELL(1.700 ns) = 2.600 ns; Loc. = LC1_B2; Fanout = 1; COMB Node = 'Equal0~109'
        Info: 3: + IC(0.900 ns) + CELL(1.600 ns) = 5.100 ns; Loc. = LC1_B1; Fanout = 16; COMB Node = 'Equal0~111'
        Info: 4: + IC(1.100 ns) + CELL(1.000 ns) = 7.200 ns; Loc. = LC2_B6; Fanout = 2; REG Node = 'TIME_OUT~reg0'
        Info: Total cell delay = 4.300 ns ( 59.72 % )
        Info: Total interconnect delay = 2.900 ns ( 40.28 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "CLK" to destination register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 13; CLK Node = 'CLK'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_B6; Fanout = 2; REG Node = 'TIME_OUT~reg0'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: - Longest clock path from clock "CLK" to source register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 13; CLK Node = 'CLK'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC8_B1; Fanout = 3; REG Node = 'lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[5]'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register "lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[12]" (data pin = "F5_IN", clock pin = "CLK") is 1.300 ns
    Info: + Longest pin to register delay is 3.100 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 13; PIN Node = 'F5_IN'
        Info: 2: + IC(0.100 ns) + CELL(1.000 ns) = 3.100 ns; Loc. = LC7_B3; Fanout = 2; REG Node = 'lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[12]'
        Info: Total cell delay = 3.000 ns ( 96.77 % )
        Info: Total interconnect delay = 0.100 ns ( 3.23 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "CLK" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 13; CLK Node = 'CLK'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC7_B3; Fanout = 2; REG Node = 'lpm_counter:COUNT_rtl_0|alt_counter_f10ke:wysi_counter|q[12]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
Info: tco from clock "CLK" to destination pin "TIME_OUT" through register "TIME_OUT~reg0" is 10.400 ns
    Info: + Longest clock path from clock "CLK" to source register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_55; Fanout = 13; CLK Node = 'CLK'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC2_B6; Fanout = 2; REG Node = 'TIME_OUT~reg0'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest register to pin delay is 7.500 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_B6; Fanout = 2; REG Node = 'TIME_OUT~reg0'
        Info: 2: + IC(1.200