csc_top.pcf

采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件.

"CSC_module/y_cst_g[22]" BEL "CSC_module/cr_green_blue[0]" BEL 
"CSC_module/cr_green_blue[1]" BEL "CSC_module/cr_green_blue[2]" BEL 
"CSC_module/cr_green_blue[3]" BEL "CSC_module/cr_green_blue[4]" BEL 
"CSC_module/cr_green_blue[5]" BEL "CSC_module/cr_green_blue[6]" BEL 
"CSC_module/y_cst_g[0]" BEL "CSC_module/y_cst_g[1]" BEL "CSC_module/y_cst_g[2]" 
BEL "CSC_module/y_cst_g[3]" BEL "CSC_module/y_cst_g[4]" BEL 
"CSC_module/y_cst_g[5]" BEL "CSC_module/y_cst_g[6]" BEL "CSC_module/y_cst_g[7]" 
BEL "CSC_module/y_cst_g[8]" BEL "CSC_module/y_cst_g[9]" BEL 
"CSC_module/y_cst_g[10]" BEL "CSC_module/y_cst_g[11]" BEL 
"CSC_module/y_cst_g[12]" BEL "CSC_module/y_cst_g[13]" BEL 
"CSC_module/y_cst_g[14]" BEL "CSC_module/cb_cst_b[6]" BEL 
"CSC_module/cb_cst_b[7]" BEL "CSC_module/cb_cst_b[8]" BEL 
"CSC_module/cb_cst_b[9]" BEL "CSC_module/cb_cst_b[10]" BEL 
"CSC_module/cb_cst_b[11]" BEL "CSC_module/cb_cst_b[12]" BEL 
"CSC_module/cb_cst_b[13]" BEL "CSC_module/cb_cst_b[14]" BEL 
"CSC_module/cb_cst_b[15]" BEL "CSC_module/cb_cst_b[16]" BEL 
"CSC_module/cb_cst_b[17]" BEL "CSC_module/cb_cst_b[18]" BEL 
"CSC_module/cb_cst_b[19]" BEL "CSC_module/cb_cst_b[20]" BEL 
"CSC_module/cb_full[12]" BEL "CSC_module/cb_full[13]" BEL 
"CSC_module/cb_full[14]" BEL "CSC_module/cb_full[15]" BEL 
"CSC_module/cb_full[16]" BEL "CSC_module/cb_full[17]" BEL 
"CSC_module/cb_full[18]" BEL "CSC_module/cb_full[19]" BEL 
"CSC_module/cb_full[20]" BEL "CSC_module/cb_cst_b[0]" BEL 
"CSC_module/cb_cst_b[1]" BEL "CSC_module/cb_cst_b[2]" BEL 
"CSC_module/cb_cst_b[3]" BEL "CSC_module/cb_cst_b[4]" BEL 
"CSC_module/cb_cst_b[5]" BEL "CSC_module/cr_cst_r[6]" BEL 
"CSC_module/cr_cst_r[7]" BEL "CSC_module/cr_cst_r[8]" BEL 
"CSC_module/cr_cst_r[9]" BEL "CSC_module/cr_cst_r[10]" BEL 
"CSC_module/cr_cst_r[11]" BEL "CSC_module/cr_cst_r[12]" BEL 
"CSC_module/cr_cst_r[13]" BEL "CSC_module/cr_cst_r[14]" BEL 
"CSC_module/cr_cst_r[15]" BEL "CSC_module/cr_cst_r[16]" BEL 
"CSC_module/cr_cst_r[17]" BEL "CSC_module/cr_cst_r[18]" BEL 
"CSC_module/cr_cst_r[19]" BEL "CSC_module/cb_full[11]" BEL 
"CSC_module/cr_full[11]" BEL "CSC_module/cr_full[12]" BEL 
"CSC_module/cr_full[13]" BEL "CSC_module/cr_full[14]" BEL 
"CSC_module/cr_full[15]" BEL "CSC_module/cr_full[16]" BEL 
"CSC_module/cr_full[17]" BEL "CSC_module/cr_full[18]" BEL 
"CSC_module/cr_full[19]" BEL "CSC_module/cr_cst_r[1]" BEL 
"CSC_module/cr_cst_r[2]" BEL "CSC_module/cr_cst_r[3]" BEL 
"CSC_module/cr_cst_r[4]" BEL "CSC_module/cr_cst_r[5]" BEL 
"CSC_module/cr_full[10]" BEL "CSC_module/Y601_KCM_red/Color_Out[18]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[19]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[20]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[21]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[22]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[3]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[4]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[5]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[6]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[7]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[8]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[9]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[10]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[11]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[12]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[13]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[14]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[15]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[16]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[17]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[10]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[11]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[12]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[13]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[14]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[15]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[16]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[17]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[18]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[19]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[20]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[21]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[22]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[3]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[4]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[5]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[6]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[7]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[8]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[9]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[17]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[18]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[19]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[20]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[2]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[3]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[4]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[5]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[6]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[7]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[8]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[9]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[10]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[11]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[12]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[13]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[14]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[15]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[16]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[1]" BEL "CSC_module/Cb_KCM_red/Color_Out[9]"
 BEL "CSC_module/Cb_KCM_red/Color_Out[10]" BEL 
"CSC_module/Cb_KCM_red/Color_Out[11]" BEL "CSC_module/Cb_KCM_red/Color_Out[12]" 
BEL "CSC_module/Cb_KCM_red/Color_Out[13]" BEL 
"CSC_module/Cb_KCM_red/Color_Out[14]" BEL "CSC_module/Cb_KCM_red/Color_Out[15]" 
BEL "CSC_module/Cb_KCM_red/Color_Out[16]" BEL 
"CSC_module/Cb_KCM_red/Color_Out[17]" BEL "CSC_module/Cb_KCM_red/Color_Out[18]" 
BEL "CSC_module/Cb_KCM_red/Color_Out[19]" BEL 
"CSC_module/Cb_KCM_red/Color_Out[20]" BEL "CSC_module/Cb_KCM_red/Color_Out[1]" 
BEL "CSC_module/Cb_KCM_red/Color_Out[2]" BEL 
"CSC_module/Cb_KCM_red/Color_Out[3]" BEL "CSC_module/Cb_KCM_red/Color_Out[4]" 
BEL "CSC_module/Cb_KCM_red/Color_Out[5]" BEL 
"CSC_module/Cb_KCM_red/Color_Out[6]" BEL "CSC_module/Cb_KCM_red/Color_Out[7]" 
BEL "CSC_module/Cb_KCM_red/Color_Out[8]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[18]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[19]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[20]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[4]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[5]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[6]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[7]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[8]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[9]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[10]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[11]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[12]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[13]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[14]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[15]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[16]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[17]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[12]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[13]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[14]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[15]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[16]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[17]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[18]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[19]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[20]" BEL "CSC_module/Cb_KCM_blue/Color_Out[0]"
 BEL "CSC_module/Cb_KCM_blue/Color_Out[1]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[2]" BEL "CSC_module/Cb_KCM_blue/Color_Out[3]" 
BEL "CSC_module/Cb_KCM_blue/Color_Out[4]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[5]" BEL "CSC_module/Cb_KCM_blue/Color_Out[6]" 
BEL "CSC_module/Cb_KCM_blue/Color_Out[7]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[8]" BEL "CSC_module/Cb_KCM_blue/Color_Out[9]" 
BEL "CSC_module/Cb_KCM_blue/Color_Out[10]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[11]" BEL "CSC_module/Cr_KCM_red/Color_Out[6]" 
BEL "CSC_module/Cr_KCM_red/Color_Out[7]" BEL 
"CSC_module/Cr_KCM_red/Color_Out[8]" BEL "CSC_module/Cr_KCM_red/Color_Out[9]" 
BEL "CSC_module/Cr_KCM_red/Color_Out[10]" BEL 
"CSC_module/Cr_KCM_red/Color_Out[11]" BEL "CSC_module/Cr_KCM_red/Color_Out[12]" 
BEL "CSC_module/Cr_KCM_red/Color_Out[13]" BEL 
"CSC_module/Cr_KCM_red/Color_Out[14]" BEL "CSC_module/Cr_KCM_red/Color_Out[15]" 
BEL "CSC_module/Cr_KCM_red/Color_Out[16]" BEL 
"CSC_module/Cr_KCM_red/Color_Out[17]" BEL "CSC_module/Cr_KCM_red/Color_Out[18]" 
BEL "CSC_module/Cr_KCM_red/Color_Out[19]" BEL 
"CSC_module/Cr_KCM_red/Color_Out[1]" BEL "CSC_module/Cr_KCM_red/Color_Out[2]" 
BEL "CSC_module/Cr_KCM_red/Color_Out[3]" BEL 
"CSC_module/Cr_KCM_red/Color_Out[4]" BEL "CSC_module/Cr_KCM_red/Color_Out[5]" 
BEL "CSC_module/Cr_KCM_green/Color_Out[16]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[17]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[18]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[19]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[1]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[2]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[3]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[4]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[5]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[6]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[7]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[8]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[9]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[10]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[11]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[12]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[13]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[14]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[15]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[0]" BEL "CSC_module/Cr_KCM_blue/Color_Out[6]"
 BEL "CSC_module/Cr_KCM_blue/Color_Out[7]" BEL 
"CSC_module/Cr_KCM_blue/Color_Out[8]" BEL "CSC_module/Cr_KCM_blue/Color_Out[9]" 
BEL "CSC_module/Cr_KCM_blue/Color_Out[10]" BEL 
"CSC_module/Cr_KCM_blue/Color_Out[11]" BEL 
"CSC_module/Cr_KCM_blue/Color_Out[12]" BEL 
"CSC_module/Cr_KCM_blue/Color_Out[13]" BEL 
"CSC_module/Cr_KCM_blue/Color_Out[14]" BEL 
"CSC_module/Cr_KCM_blue/Color_Out[15]" BEL 
"CSC_module/Cr_KCM_blue/Color_Out[16]" BEL "CSC_module/Cr_KCM_blue/Color_Out[1]"
 BEL "CSC_module/Cr_KCM_blue/Color_Out[2]" BEL 
"CSC_module/Cr_KCM_blue/Color_Out[3]" BEL "CSC_module/Cr_KCM_blue/Color_Out[4]" 
BEL "CSC_module/Cr_KCM_blue/Color_Out[5]" ;
OFFSET = IN 9.500 nS  BEFORE COMP "Clock" ;
OFFSET = OUT 9.500 nS  AFTER COMP "Clock" ;
SCHEMATIC END ;