csc_top_virtex.ucf

采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件.

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NET "Clock" LOC = "P93"  ;
INST "Clock_ibuf" LOC = "GCLKBUF1"  ;
NET "ClockEnable" LOC = "P131"  ;
NET "Reset" LOC = "P33"  ;
#
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NET "Red(9)" LOC = "P119"  ;
NET "Red(8)" LOC = "P118"  ;
NET "Red(7)" LOC = "P116"  ;
NET "Red(6)" LOC = "P107"  ;
NET "Red(5)" LOC = "P134"  ;
NET "Red(4)" LOC = "P117"  ;
NET "Red(3)" LOC = "P98"  ;
NET "Red(2)" LOC = "P115"  ;
NET "Red(1)" LOC = "P97"  ;
NET "Red(0)" LOC = "P106"  ;
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NET "Green(9)" LOC = "P41"  ;
NET "Green(8)" LOC = "P39"  ;
NET "Green(7)" LOC = "P43"  ;
NET "Green(6)" LOC = "P42"  ;
NET "Green(5)" LOC = "P27"  ;
NET "Green(4)" LOC = "P40"  ;
NET "Green(3)" LOC = "P82"  ;
NET "Green(2)" LOC = "P85"  ;
NET "Green(1)" LOC = "P86"  ;
NET "Green(0)" LOC = "P81"  ;
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NET "Blue(9)" LOC = "P142"  ;
NET "Blue(8)" LOC = "P5"  ;
NET "Blue(7)" LOC = "P138"  ;
NET "Blue(6)" LOC = "P4"  ;
NET "Blue(5)" LOC = "P8"  ;
NET "Blue(4)" LOC = "P7"  ;
NET "Blue(3)" LOC = "P103"  ;
NET "Blue(2)" LOC = "P104"  ;
NET "Blue(1)" LOC = "P140"  ;
NET "Blue(0)" LOC = "P3"  ;
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NET "Y(9)" LOC = "P13"  ;
NET "Y(8)" LOC = "P96"  ;
NET "Y(7)" LOC = "P24"  ;
NET "Y(6)" LOC = "P23"  ;
NET "Y(5)" LOC = "P95"  ;
NET "Y(4)" LOC = "P89"  ;
NET "Y(3)" LOC = "P28"  ;
NET "Y(2)" LOC = "P88"  ;
NET "Y(1)" LOC = "P101"  ;
NET "Y(0)" LOC = "P102"  ;
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NET "Cb(9)" LOC = "P12"  ;
NET "Cb(8)" LOC = "P11"  ;
NET "Cb(7)" LOC = "P14"  ;
NET "Cb(6)" LOC = "P141"  ;
NET "Cb(5)" LOC = "P20"  ;
NET "Cb(4)" LOC = "P139"  ;
NET "Cb(3)" LOC = "P137"  ;
NET "Cb(2)" LOC = "P21"  ;
NET "Cb(1)" LOC = "P6"  ;
NET "Cb(0)" LOC = "P22"  ;
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NET "Cr(9)" LOC = "P132"  ;
NET "Cr(8)" LOC = "P133"  ;
NET "Cr(7)" LOC = "P130"  ;
NET "Cr(6)" LOC = "P135"  ;
NET "Cr(5)" LOC = "P125"  ;
NET "Cr(4)" LOC = "P127"  ;
NET "Cr(3)" LOC = "P123"  ;
NET "Cr(2)" LOC = "P124"  ;
NET "Cr(1)" LOC = "P121"  ;
NET "Cr(0)" LOC = "P122"  ;
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