📄 csc_top.par
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Release 4.2.03i - Par E.38Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Fri Aug 02 15:18:53 2002par -w -detail -l 5 csc_top_map.ncd csc_top.ncd csc_top.pcfConstraints file: csc_top.pcfLoading design for application par from file csc_top_map.ncd. "csc_top" is an NCD, version 2.37, device xc2s50e, package tq144, speed -6Loading device for application par from file '2s50e.nph' in environment
C:/ISE42.Device speed data version: PRELIMINARY 1.11 2002-05-10.Device utilization summary: Number of External GCLKIOBs 1 out of 4 25% Number of External IOBs 62 out of 98 63% Number of LOCed External IOBs 0 out of 62 0% Number of SLICEs 283 out of 768 36% Number of GCLKs 1 out of 4 25%Overall effort level (-ol): 5 (set by user)Placer effort level (-pl): 5 (default)Placer cost table entry (-t): 1Router effort level (-rl): 5 (default)Extra effort level (-xe): 1 (default)Starting initial Timing Analysis. REAL time: 8 secs Finished initial Timing Analysis. REAL time: 11 secs Starting initial Placement phase. REAL time: 13 secs Finished initial Placement phase. REAL time: 13 secs Starting the placer. REAL time: 13 secs Placement pass 1 ..Placer score = 53215Placement pass 2 ....Placer score = 56365Placement pass 3 ..........................Placer score = 56560Placement pass 4 .................Placer score = 51468Placement pass 5 .........................Placer score = 57978Placement pass 6 .......................Placer score = 53930Optimizing ... Placer score = 51185Placer score = 51345Placer score = 51652Placer score = 51712Placer score = 51369Placer score = 51398Placer score = 51553Placer score = 51372Placer score = 51556Placer score = 51243Placer score = 50913Placer score = 50836Placer score = 50928Placer score = 50806Placer score = 50776Placer score = 50733Placer score = 50701Placer score = 50671Placer score = 50626Placer score = 50628Placer score = 50626Placer stage completed in real time: 21 secs Optimizing ... Placer score = 45546Placer completed in real time: 21 secs Dumping design to file csc_top.ncd.Total REAL time to Placer completion: 22 secs Total CPU time to Placer completion: 6 secs 0 connection(s) routed; 1783 unrouted active, 37 unrouted PWR/GND.Starting router resource preassignmentCompleted router resource preassignment. REAL time: 23 secs Starting iterative routing. Routing active signals............Optimizing (1118).............................................................................................................End of iteration 1 1820 successful; 0 unrouted; (816) REAL time: 1 mins 3 secs .End of iteration 2 1820 successful; 0 unrouted; (816) REAL time: 1 mins 37 secs WARNING:Route:260 - Routing for this placement is not expected to meet the
current timing constraints. Change the placement, modify the timing
constraints or reduce the number of logic levels in the paths that are not
meeting timing.Total REAL time: 1 mins 37 secs Total CPU time: 26 secs End of route. 1820 routed (100.00%); 0 unrouted.No errors found. Completely routed. The design submitted for place and route did not meet the specified timing
requirements. Please use the static timing analysis tools (TRCE or Timing
Analyzer) to report which constraints were not met. To obtain a better result,
you may try the following: * Use the Re-entrant routing feature to run more router iterations on the
design. * Check the timing constraints to make sure the design is not
over-constrained. * Specify a higher placer effort level, if possible. * Use the Multi-Pass PAR (MPPR) feature. This generates multiple placement
trials from which the best (i.e., lowest design score) placement can be used
with re-entrant routing to obtain a better result.Please consult the Development System Reference Guide for more detailed
information about the usage options pertaining to these features.Total REAL time to Router completion: 1 mins 38 secs Total CPU time to Router completion: 27 secs Generating PAR statistics. The Delay Summary Report The Score for this design is: 1300The Number of signals not completely routed for this design is: 0 The Average Connection Delay for this design is: 1.888 ns The Maximum Pin Delay is: 6.476 ns The Average Connection Delay on the 10 Worst Nets is: 4.775 ns Listing Pin Delays by value: (ns) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 7.00 d >= 7.00 --------- --------- --------- --------- --------- --------- 694 415 246 250 215 0Timing Score: 816WARNING:Par:62 - Timing constraints have not been met.Asterisk (*) preceding a constraint indicates it was not met.-------------------------------------------------------------------------------- Constraint | Requested | Actual | Logic | | | Levels--------------------------------------------------------------------------------* NET "Clock_ibuf/IBUFG" PERIOD = 12.500 n | 12.500ns | 13.316ns | 13 S HIGH 50.000000 % | | | -------------------------------------------------------------------------------- OFFSET = IN 9.500 nS BEFORE COMP "Clock" | 9.500ns | 7.257ns | 3 -------------------------------------------------------------------------------- OFFSET = OUT 9.500 nS AFTER COMP "Clock" | 9.500ns | 6.465ns | 1 --------------------------------------------------------------------------------1 constraint not met.Dumping design to file csc_top.ncd.All signals are completely routed.Total REAL time to PAR completion: 1 mins 43 secs Total CPU time to PAR completion: 27 secs Placement: Completed - No errors found.Routing: Completed - No errors found.Timing: Completed - 1 errors found.PAR done.⌨️ 快捷键说明
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