csc_top.par

采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件.

Release 4.2.03i - Par E.38
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


Fri Aug 02 15:15:08 2002

par -w -detail -l 5 csc_top_map.ncd csc_top.ncd csc_top.pcf


Constraints file: csc_top.pcf

Loading design for application par from file csc_top_map.ncd.
   "csc_top" is an NCD, version 2.37, device xc2vp2, package fg256, speed -6
Loading device for application par from file '2vp2.nph' in environment C:/ISE42.
Device speed data version:  ADVANCED 1.56 2002-05-15.


Device utilization summary:

   Number of External IOBs            63 out of 140    45%
      Number of LOCed External IOBs    0 out of 63      0%

   Number of SLICEs                  178 out of 1408   12%

   Number of BUFGMUXs                  1 out of 16      6%



Overall effort level (-ol):   5 (set by user)
Placer effort level (-pl):    5 (default)
Placer cost table entry (-t): 1
Router effort level (-rl):    5 (default)
Extra effort level (-xe):     1 (default)

Starting initial Timing Analysis.  REAL time: 8 secs 
Finished initial Timing Analysis.  REAL time: 10 secs 

Starting Clock Logic Placement.  REAL time: 11 secs 

Finished Clock Logic Placement.  REAL time: 11 secs 

Automatic resolution of clock placement was successful.
It was not necessary to constrain the placement of any of the logic driven by
the global clocks with the current clock placement.

######################################################
## Automatic clock placement completed.
######################################################

Starting clustering phase.  REAL time: 23 secs 
Finished clustering phase.  REAL time: 23 secs 

Dumping design to file csc_top.ncd.

Starting Directed Placer.  REAL time: 24 secs 
Placement pass 1 .

Placer score = 61965
Placer score = 61965
Finished Directed Placer.  REAL time: 25 secs 

Starting Constructive Placer.  REAL time: 25 secs 
Placer score = 49570
Placer score = 46385
Finished Constructive Placer.  REAL time: 25 secs 

Dumping design to file csc_top.ncd.

Starting Optimizing Placer.  REAL time: 25 secs 
Optimizing  
Swapped 51 comps.
Xilinx Placer [1]   44085   REAL time: 25 secs 
Optimizing  
Swapped 5 comps.
Xilinx Placer [2]   44025   REAL time: 26 secs 
Finished Optimizing Placer.  REAL time: 26 secs 

Dumping design to file csc_top.ncd.

Total REAL time to Placer completion: 26 secs 
Total CPU time to Placer completion: 10 secs 

0 connection(s) routed; 1492 unrouted active, 23 unrouted PWR/GND.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 26 secs 
Starting iterative routing. 
Routing active signals.
..........
End of iteration 1 
1515 successful; 0 unrouted; (0) REAL time: 29 secs 
Constraints are met. 
Total REAL time: 29 secs 
Total CPU  time: 13 secs 
End of route.  1515 routed (100.00%); 0 unrouted.
No errors found. 
WARNING:Route:49 - The signal "GLOBAL_LOGIC0" has no loads so was not routed. 

Total REAL time to Router completion: 30 secs 
Total CPU time to Router completion: 13 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 5150


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        0.896 ns
   The Maximum Pin Delay is:                               5.028 ns
   The Average Connection Delay on the 10 Worst Nets is:   3.066 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
         914         426         131          37           7           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "Clock_ibuf/IBUFG" PERIOD =  12.500 n | 12.500ns   | 7.170ns    | 9    
  S   HIGH 50.000000 %                      |            |            |      
--------------------------------------------------------------------------------
  OFFSET = IN 9.500 nS  BEFORE COMP "Clock" | 9.500ns    | 3.846ns    | 3    
--------------------------------------------------------------------------------
  OFFSET = OUT 9.500 nS  AFTER COMP "Clock" | 9.500ns    | 6.285ns    | 1    
--------------------------------------------------------------------------------


All constraints were met.
Dumping design to file csc_top.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 31 secs 
Total CPU time to PAR completion: 14 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

PAR done.