csc_top.par

采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件.

Release 4.2.03i - Par E.38
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


Fri Aug 02 15:14:26 2002

par -w -detail -l 5 csc_top_map.ncd csc_top.ncd csc_top.pcf


Constraints file: csc_top.pcf

Loading design for application par from file csc_top_map.ncd.
   "csc_top" is an NCD, version 2.37, device xc2s50e, package tq144, speed -6
Loading device for application par from file '2s50e.nph' in environment
C:/ISE42.
Device speed data version:  PRELIMINARY 1.11 2002-05-10.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            62 out of 98     63%
      Number of LOCed External IOBs    0 out of 62      0%

   Number of SLICEs                  173 out of 768    22%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   5 (set by user)
Placer effort level (-pl):    5 (default)
Placer cost table entry (-t): 1
Router effort level (-rl):    5 (default)
Extra effort level (-xe):     1 (default)

Starting initial Timing Analysis.  REAL time: 2 secs 
Finished initial Timing Analysis.  REAL time: 3 secs 

Starting initial Placement phase. REAL time: 4 secs 
Finished initial Placement phase. REAL time: 4 secs 
Starting the placer. REAL time: 4 secs 
Placement pass 1 .
Placer score = 38230
Placement pass 2 .
Placer score = 37071
Optimizing ... 
Placer score = 36235
Placer score = 36670
Placer score = 36625
Placer score = 36415
Placer score = 36535
Placer score = 36250
Placer score = 36250
Placer score = 36205
Placer score = 36190
Placer score = 36100
Placer score = 36055
Placer score = 36040
Placer score = 36010
Placer score = 36010
Placer score = 35950
Placer score = 35950
Placer stage completed in real time: 5 secs 

Optimizing ... 
Placer score = 32305
Placer completed in real time: 6 secs 

Dumping design to file csc_top.ncd.

Total REAL time to Placer completion: 6 secs 
Total CPU time to Placer completion: 3 secs 

0 connection(s) routed; 1267 unrouted active, 24 unrouted PWR/GND.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 7 secs 
Starting iterative routing. 
Routing active signals.
.......
End of iteration 1 
1291 successful; 0 unrouted; (0) REAL time: 11 secs 
Constraints are met. 
Total REAL time: 11 secs 
Total CPU  time: 5 secs 
End of route.  1291 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

Total REAL time to Router completion: 11 secs 
Total CPU time to Router completion: 5 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 275


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        1.876 ns
   The Maximum Pin Delay is:                               6.053 ns
   The Average Connection Delay on the 10 Worst Nets is:   4.370 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 7.00  d >= 7.00
   ---------   ---------   ---------   ---------   ---------   ---------
         472         321         181         143         174           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "Clock_ibuf/IBUFG" PERIOD =  12.500 n | 12.500ns   | 10.605ns   | 8    
  S   HIGH 50.000000 %                      |            |            |      
--------------------------------------------------------------------------------
  OFFSET = IN 9.500 nS  BEFORE COMP "Clock" | 9.500ns    | 7.417ns    | 3    
--------------------------------------------------------------------------------
  OFFSET = OUT 9.500 nS  AFTER COMP "Clock" | 9.500ns    | 6.453ns    | 1    
--------------------------------------------------------------------------------


All constraints were met.
Dumping design to file csc_top.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 13 secs 
Total CPU time to PAR completion: 6 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

PAR done.