csc_top.pcf

采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件.

SCHEMATIC START ;
// created by map version E.38 on Fri Aug 02 15:14:25 2002 
NET "Clock_ibuf/IBUFG" PERIOD =  12.500 nS   HIGH 50.000000 % ;
TIMEGRP "Clock" = BEL "g[4]" BEL "g[5]" BEL "g[6]" BEL "g[7]" BEL "g[8]" BEL 
"g[9]" BEL "Cb[9]" BEL "r[0]" BEL "r[1]" BEL "r[2]" BEL "r[3]" BEL "r[4]" BEL 
"r[5]" BEL "r[6]" BEL "r[7]" BEL "r[8]" BEL "r[9]" BEL "g[0]" BEL "g[1]" BEL 
"g[2]" BEL "g[3]" BEL "Cr[4]" BEL "Cr[5]" BEL "Cr[6]" BEL "Cr[7]" BEL "Cr[8]" 
BEL "Cr[9]" BEL "Cb[0]" BEL "Cb[1]" BEL "Cb[2]" BEL "Cb[3]" BEL "Cb[4]" BEL 
"Cb[5]" BEL "Cb[6]" BEL "Cb[7]" BEL "Cb[8]" BEL "Y[0]" BEL "Y[1]" BEL "Y[2]" 
BEL "Y[3]" BEL "Y[4]" BEL "Y[5]" BEL "Y[6]" BEL "Y[7]" BEL "Y[8]" BEL "Y[9]" 
BEL "Cr[0]" BEL "Cr[1]" BEL "Cr[2]" BEL "Cr[3]" BEL "b[0]" BEL "b[1]" BEL "b[2]"
 BEL "b[3]" BEL "b[4]" BEL "b[5]" BEL "b[6]" BEL "b[7]" BEL "b[8]" BEL "b[9]" 
BEL "CSC_module/y_red_blue[17]" BEL "CSC_module/y_red_blue[2]" BEL 
"CSC_module/y_red_blue[3]" BEL "CSC_module/y_red_blue[4]" BEL 
"CSC_module/y_red_blue[5]" BEL "CSC_module/y_red_blue[6]" BEL 
"CSC_module/y_red_blue[7]" BEL "CSC_module/y_red_blue[8]" BEL 
"CSC_module/y_red_blue[9]" BEL "CSC_module/y_red_blue[10]" BEL 
"CSC_module/y_red_blue[11]" BEL "CSC_module/y_red_blue[12]" BEL 
"CSC_module/y_red_blue[13]" BEL "CSC_module/y_red_blue[14]" BEL 
"CSC_module/y_red_blue[15]" BEL "CSC_module/y_red_blue[16]" BEL 
"CSC_module/cb_red_green[15]" BEL "CSC_module/cb_red_green[16]" BEL 
"CSC_module/cb_red_green[17]" BEL "CSC_module/y601_full[8]" BEL 
"CSC_module/y601_full[9]" BEL "CSC_module/y601_full[10]" BEL 
"CSC_module/y601_full[11]" BEL "CSC_module/y601_full[12]" BEL 
"CSC_module/y601_full[13]" BEL "CSC_module/y601_full[14]" BEL 
"CSC_module/y601_full[15]" BEL "CSC_module/y601_full[16]" BEL 
"CSC_module/y601_full[17]" BEL "CSC_module/y_red_blue[0]" BEL 
"CSC_module/y_red_blue[1]" BEL "CSC_module/cb_red_green[1]" BEL 
"CSC_module/cb_red_green[2]" BEL "CSC_module/cb_red_green[3]" BEL 
"CSC_module/cb_red_green[4]" BEL "CSC_module/cb_red_green[5]" BEL 
"CSC_module/cb_red_green[6]" BEL "CSC_module/cb_red_green[7]" BEL 
"CSC_module/cb_red_green[8]" BEL "CSC_module/cb_red_green[9]" BEL 
"CSC_module/cb_red_green[10]" BEL "CSC_module/cb_red_green[11]" BEL 
"CSC_module/cb_red_green[12]" BEL "CSC_module/cb_red_green[13]" BEL 
"CSC_module/cb_red_green[14]" BEL "CSC_module/cr_green_blue[3]" BEL 
"CSC_module/cr_green_blue[4]" BEL "CSC_module/cr_green_blue[5]" BEL 
"CSC_module/cr_green_blue[6]" BEL "CSC_module/cr_green_blue[7]" BEL 
"CSC_module/cr_green_blue[8]" BEL "CSC_module/cr_green_blue[9]" BEL 
"CSC_module/cr_green_blue[10]" BEL "CSC_module/cr_green_blue[11]" BEL 
"CSC_module/cr_green_blue[12]" BEL "CSC_module/cr_green_blue[13]" BEL 
"CSC_module/cr_green_blue[14]" BEL "CSC_module/cr_green_blue[15]" BEL 
"CSC_module/cr_green_blue[16]" BEL "CSC_module/cr_green_blue[17]" BEL 
"CSC_module/y_cst_g[6]" BEL "CSC_module/y_cst_g[7]" BEL "CSC_module/y_cst_g[8]" 
BEL "CSC_module/y_cst_g[9]" BEL "CSC_module/y_cst_g[10]" BEL 
"CSC_module/y_cst_g[11]" BEL "CSC_module/y_cst_g[12]" BEL 
"CSC_module/y_cst_g[13]" BEL "CSC_module/y_cst_g[14]" BEL 
"CSC_module/y_cst_g[15]" BEL "CSC_module/y_cst_g[16]" BEL 
"CSC_module/y_cst_g[17]" BEL "CSC_module/cr_green_blue[1]" BEL 
"CSC_module/cr_green_blue[2]" BEL "CSC_module/cb_cst_b[9]" BEL 
"CSC_module/cb_cst_b[10]" BEL "CSC_module/cb_cst_b[11]" BEL 
"CSC_module/cb_cst_b[12]" BEL "CSC_module/cb_cst_b[13]" BEL 
"CSC_module/cb_cst_b[14]" BEL "CSC_module/cb_cst_b[15]" BEL 
"CSC_module/cb_cst_b[16]" BEL "CSC_module/cb_cst_b[17]" BEL 
"CSC_module/y_cst_g[0]" BEL "CSC_module/y_cst_g[1]" BEL "CSC_module/y_cst_g[2]" 
BEL "CSC_module/y_cst_g[3]" BEL "CSC_module/y_cst_g[4]" BEL 
"CSC_module/y_cst_g[5]" BEL "CSC_module/cb_full[12]" BEL 
"CSC_module/cb_full[13]" BEL "CSC_module/cb_full[14]" BEL 
"CSC_module/cb_full[15]" BEL "CSC_module/cb_full[16]" BEL 
"CSC_module/cb_full[17]" BEL "CSC_module/cb_cst_b[4]" BEL 
"CSC_module/cb_cst_b[5]" BEL "CSC_module/cb_cst_b[6]" BEL 
"CSC_module/cb_cst_b[7]" BEL "CSC_module/cb_cst_b[8]" BEL 
"CSC_module/cr_cst_r[7]" BEL "CSC_module/cr_cst_r[8]" BEL 
"CSC_module/cr_cst_r[9]" BEL "CSC_module/cr_cst_r[10]" BEL 
"CSC_module/cr_cst_r[11]" BEL "CSC_module/cr_cst_r[12]" BEL 
"CSC_module/cr_cst_r[13]" BEL "CSC_module/cr_cst_r[14]" BEL 
"CSC_module/cr_cst_r[15]" BEL "CSC_module/cr_cst_r[16]" BEL 
"CSC_module/cr_cst_r[17]" BEL "CSC_module/cb_full[8]" BEL 
"CSC_module/cb_full[9]" BEL "CSC_module/cb_full[10]" BEL 
"CSC_module/cb_full[11]" BEL "CSC_module/cr_full[10]" BEL 
"CSC_module/cr_full[11]" BEL "CSC_module/cr_full[12]" BEL 
"CSC_module/cr_full[13]" BEL "CSC_module/cr_full[14]" BEL 
"CSC_module/cr_full[15]" BEL "CSC_module/cr_full[16]" BEL 
"CSC_module/cr_full[17]" BEL "CSC_module/cr_cst_r[4]" BEL 
"CSC_module/cr_cst_r[5]" BEL "CSC_module/cr_cst_r[6]" BEL 
"CSC_module/cr_full[8]" BEL "CSC_module/cr_full[9]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[9]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[10]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[11]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[12]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[13]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[14]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[15]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[16]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[2]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[3]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[4]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[5]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[6]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[7]" BEL 
"CSC_module/Y601_KCM_red/Color_Out[8]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[6]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[7]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[8]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[9]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[10]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[11]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[12]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[13]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[14]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[15]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[16]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[17]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[2]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[3]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[4]" BEL 
"CSC_module/Y601_KCM_green/Color_Out[5]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[3]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[4]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[5]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[6]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[7]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[8]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[9]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[10]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[11]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[12]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[13]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[14]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[1]" BEL 
"CSC_module/Y601_KCM_blue/Color_Out[2]" BEL 
"CSC_module/Cb_KCM_red/Color_Out[15]" BEL "CSC_module/Cb_KCM_red/Color_Out[2]" 
BEL "CSC_module/Cb_KCM_red/Color_Out[3]" BEL 
"CSC_module/Cb_KCM_red/Color_Out[4]" BEL "CSC_module/Cb_KCM_red/Color_Out[5]" 
BEL "CSC_module/Cb_KCM_red/Color_Out[6]" BEL 
"CSC_module/Cb_KCM_red/Color_Out[7]" BEL "CSC_module/Cb_KCM_red/Color_Out[8]" 
BEL "CSC_module/Cb_KCM_red/Color_Out[9]" BEL 
"CSC_module/Cb_KCM_red/Color_Out[10]" BEL "CSC_module/Cb_KCM_red/Color_Out[11]" 
BEL "CSC_module/Cb_KCM_red/Color_Out[12]" BEL 
"CSC_module/Cb_KCM_red/Color_Out[13]" BEL "CSC_module/Cb_KCM_red/Color_Out[14]" 
BEL "CSC_module/Cb_KCM_green/Color_Out[12]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[13]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[14]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[15]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[16]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[2]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[3]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[4]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[5]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[6]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[7]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[8]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[9]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[10]" BEL 
"CSC_module/Cb_KCM_green/Color_Out[11]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[9]" BEL "CSC_module/Cb_KCM_blue/Color_Out[10]"
 BEL "CSC_module/Cb_KCM_blue/Color_Out[11]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[12]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[13]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[14]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[15]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[16]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[17]" BEL "CSC_module/Cb_KCM_blue/Color_Out[4]"
 BEL "CSC_module/Cb_KCM_blue/Color_Out[5]" BEL 
"CSC_module/Cb_KCM_blue/Color_Out[6]" BEL "CSC_module/Cb_KCM_blue/Color_Out[7]" 
BEL "CSC_module/Cb_KCM_blue/Color_Out[8]" BEL 
"CSC_module/Cr_KCM_red/Color_Out[6]" BEL "CSC_module/Cr_KCM_red/Color_Out[7]" 
BEL "CSC_module/Cr_KCM_red/Color_Out[8]" BEL 
"CSC_module/Cr_KCM_red/Color_Out[9]" BEL "CSC_module/Cr_KCM_red/Color_Out[10]" 
BEL "CSC_module/Cr_KCM_red/Color_Out[11]" BEL 
"CSC_module/Cr_KCM_red/Color_Out[12]" BEL "CSC_module/Cr_KCM_red/Color_Out[13]" 
BEL "CSC_module/Cr_KCM_red/Color_Out[14]" BEL 
"CSC_module/Cr_KCM_red/Color_Out[15]" BEL "CSC_module/Cr_KCM_red/Color_Out[16]" 
BEL "CSC_module/Cr_KCM_red/Color_Out[17]" BEL 
"CSC_module/Cr_KCM_red/Color_Out[4]" BEL "CSC_module/Cr_KCM_red/Color_Out[5]" 
BEL "CSC_module/Cr_KCM_green/Color_Out[3]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[4]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[5]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[6]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[7]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[8]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[9]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[10]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[11]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[12]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[13]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[14]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[15]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[16]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[17]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[1]" BEL 
"CSC_module/Cr_KCM_green/Color_Out[2]" BEL "CSC_module/Cr_KCM_blue/Color_Out[5]"
 BEL "CSC_module/Cr_KCM_blue/Color_Out[6]" BEL 
"CSC_module/Cr_KCM_blue/Color_Out[7]" BEL "CSC_module/Cr_KCM_blue/Color_Out[8]" 
BEL "CSC_module/Cr_KCM_blue/Color_Out[9]" BEL 
"CSC_module/Cr_KCM_blue/Color_Out[10]" BEL 
"CSC_module/Cr_KCM_blue/Color_Out[11]" BEL 
"CSC_module/Cr_KCM_blue/Color_Out[12]" BEL 
"CSC_module/Cr_KCM_blue/Color_Out[13]" BEL 
"CSC_module/Cr_KCM_blue/Color_Out[14]" BEL "CSC_module/Cr_KCM_blue/Color_Out[4]"
 ;
OFFSET = IN 9.500 nS  BEFORE COMP "Clock" ;
OFFSET = OUT 9.500 nS  AFTER COMP "Clock" ;
SCHEMATIC END ;