csc_top.bld

来自「采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和veri」· BLD 代码 · 共 27 行

BLD

27 行

Release 4.2.03i - ngdbuild E.38Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -p xc2s50e-6tq144 csc_top.edn Launcher: Executing edif2ngd "csc_top.edn" "csc_top.ngo"INFO:NgdBuild - Release 4.2.03i - edif2ngd E.38INFO:NgdBuild - Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.Writing the design to "csc_top.ngo"...Reading NGO file
"C:/Designs/Designs_Projects_Cores_Tests/ColorSpaceConverter_XAPP/VHDL/Top/netli
st_10bit_8bit/Spartan2E/csc_top.ngo" ...Reading component libraries for design expansion...Annotating constraints to design from file "csc_top.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Writing NGD file "csc_top.ngd" ...Writing NGDBUILD log file "csc_top.bld"...

csc_top.bld - 源码说明

本页面展示了「采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件.」中的 csc_top.bld 源码文件，采用 BLD 编程语言编写，共 27 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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