csc_top.par

采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件.

Release 4.2.03i - Par E.38
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.


Fri Aug 02 14:58:26 2002

par -w -detail -l 5 csc_top_map.ncd csc_top.ncd csc_top.pcf


Constraints file: csc_top.pcf

Loading design for application par from file csc_top_map.ncd.
   "csc_top" is an NCD, version 2.37, device xcv50e, package cs144, speed -6
Loading device for application par from file 'v50e.nph' in environment C:/ISE42.
Device speed data version:  PRELIMINARY 1.65 2001-12-19.


Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            50 out of 94     53%
      Number of LOCed External IOBs    0 out of 50      0%

   Number of SLICEs                  150 out of 768    19%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   5 (set by user)
Placer effort level (-pl):    5 (default)
Placer cost table entry (-t): 1
Router effort level (-rl):    5 (default)
Extra effort level (-xe):     1 (default)

Starting initial Timing Analysis.  REAL time: 0 secs 
Finished initial Timing Analysis.  REAL time: 2 secs 

Starting initial Placement phase. REAL time: 2 secs 
Finished initial Placement phase. REAL time: 2 secs 
Starting the placer. REAL time: 2 secs 
Placement pass 1 .
Placer score = 28660
Placement pass 2 .
Placer score = 27547
Placement pass 3 ......
Placer score = 29362
Placement pass 4 ........
Placer score = 30592
Placement pass 5 ....
Placer score = 28876
Placement pass 6 ..
Placer score = 28841
Optimizing ... 
Placer score = 28828
Placer score = 28776
Placer score = 28652
Placer score = 28667
Placer score = 28722
Placer score = 28824
Placer score = 28705
Placer score = 28602
Placer score = 28527
Placer score = 28617
Placer score = 28555
Placer score = 28527
Placer score = 28452
Placer score = 28392
Placer score = 28347
Placer score = 28302
Placer score = 28317
Placer score = 28317
Placer score = 28302
Placer stage completed in real time: 3 secs 

Optimizing ... 
Placer score = 24760
Placer completed in real time: 3 secs 

Dumping design to file csc_top.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 3 secs 

0 connection(s) routed; 1067 unrouted active, 24 unrouted PWR/GND.
Starting router resource preassignment
Completed router resource preassignment. REAL time: 3 secs 
Starting iterative routing. 
Routing active signals.
........
End of iteration 1 
1091 successful; 0 unrouted; (0) REAL time: 5 secs 
Constraints are met. 
Total REAL time: 5 secs 
Total CPU  time: 4 secs 
End of route.  1091 routed (100.00%); 0 unrouted.
No errors found. 
Completely routed. 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 4 secs 

Generating PAR statistics.

   The Delay Summary Report

   The Score for this design is: 274


The Number of signals not completely routed for this design is: 0

   The Average Connection Delay for this design is:        1.989 ns
   The Maximum Pin Delay is:                               7.045 ns
   The Average Connection Delay on the 10 Worst Nets is:   3.787 ns

   Listing Pin Delays by value: (ns)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 8.00  d >= 8.00
   ---------   ---------   ---------   ---------   ---------   ---------
         425         247         168          74         177           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "Clock_ibuf/IBUFG" PERIOD =  12.500 n | 12.500ns   | 9.844ns    | 9    
  S   HIGH 50.000000 %                      |            |            |      
--------------------------------------------------------------------------------
  OFFSET = IN 9.500 nS  BEFORE COMP "Clock" | 9.500ns    | 7.787ns    | 3    
--------------------------------------------------------------------------------
  OFFSET = OUT 9.500 nS  AFTER COMP "Clock" | 9.500ns    | 6.447ns    | 1    
--------------------------------------------------------------------------------


All constraints were met.
Dumping design to file csc_top.ncd.


All signals are completely routed.

Total REAL time to PAR completion: 5 secs 
Total CPU time to PAR completion: 5 secs 

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

PAR done.