csc_top.ucf

采用FPGA实现色彩空间转换R’G’B’ to Y’CbCr的VHDL和verilog源代码,支持xilinx的各种器件.

#
# ************************
#   CSC constraints file
# ************************
#
# Global clock timespec
NET "Clock" TNM_NET = "Clock";
NET "Clock" PERIOD = 12.5 ns HIGH 50 %;
#
#
# Input Setup time
OFFSET = IN 9.5 ns BEFORE "Clock";
#
# Output clock-to-out time
OFFSET = OUT 9.5 ns AFTER "Clock";
#