latch_20bit.v

来自「一个验证过的CAM源码（CAM=Content Address Memory）。」· Verilog 代码 · 共 23 行

`include "definitions.v"

module latch_20bit ( data_in, data_out, phi);

// Port Declarations

input [19:0] data_in;
output [19:0] data_out;
input phi;

reg [19:0] data_out;


// latch

always @ (phi or data_in)
begin
  if (phi)
    `LATCH_DELAY data_out <= data_in;
end

endmodule // latch_20bit