mask_decode.v

一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog

module mask_decode(enc_mask_s1, data_in_s1, true_bits_s1, false_bits_s1);
   input [3:0] enc_mask_s1;
   input [14:0] data_in_s1;
   output [14:0] true_bits_s1;
   output [14:0] false_bits_s1;
   
   
   reg [14:0] 	 true_bits_s1;
   reg [14:0] 	 false_bits_s1;

   reg [14:0]    mask_bits_s1;

   always @ (enc_mask_s1 or mask_bits_s1 or data_in_s1)
     begin
	case (enc_mask_s1)
	  4'b0000: mask_bits_s1 = 15'h0000;
	  4'b0001: mask_bits_s1 = 15'h0001;
	  4'b0010: mask_bits_s1 = 15'h0003;
	  4'b0011: mask_bits_s1 = 15'h0007;
	  4'b0100: mask_bits_s1 = 15'h000f;
	  4'b0101: mask_bits_s1 = 15'h001f;
	  4'b0110: mask_bits_s1 = 15'h003f;
	  4'b0111: mask_bits_s1 = 15'h007f;
	  4'b1000: mask_bits_s1 = 15'h00ff;
	  4'b1001: mask_bits_s1 = 15'h01ff;
	  4'b1010: mask_bits_s1 = 15'h03ff;
	  4'b1011: mask_bits_s1 = 15'h07ff;
	  4'b1100: mask_bits_s1 = 15'h0fff;
	  4'b1101: mask_bits_s1 = 15'h1fff;
	  4'b1110: mask_bits_s1 = 15'h3fff;
	  4'b1111: mask_bits_s1 = 15'h7fff;

/*** _Will_ never happen because every combo is covered above ***/
/***
	  // should never happen
	  default: $display("ERROR: in mask decode at %d", $time);
 ***/
	endcase
	
	// now false_bits_s1 has decoded mask, where it has 1
	// every place the bit should be masked
	// Remember, to be masked both T and F bits must be 0
	
	// true bits are 1 when they are *not* masked, and
	// they also happen to be a 1
	true_bits_s1 = (~mask_bits_s1) & data_in_s1;
	
	// false bits are 1 when they are not masked and the
	// data in is a 0
	false_bits_s1 = (~mask_bits_s1) & (~data_in_s1);
     end
   
endmodule // mask_decode