clkgen.v

一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog

`include "definitions.v"

/////////////////////////////////////////////////////////////////////////////
module clkgen(phi1, phi2);
/////////////////////////////////////////////////////////////////////////////
  output        phi1,           // Two-phase non-overlapping clocks
                phi2;

  reg           phi1,
                phi2;
          // Start with both clocks low
  initial
    begin
      phi1 = 0;
      phi2 = 0;
    end

  // Generate two-phase non-overlapping clock waveforms
  always
    begin
      `PHI1_HIGH     phi1 <= 0;
      `NON_OVLP_1_2  phi2 <= 1;
      `PHI2_HIGH     phi2 <= 0;
      `NON_OVLP_2_1  phi1 <= 1;
    end
endmodule