control_2.v

一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog

`include "definitions.v"

// Need a Reset signal for reseting all occupied bits of CAM

module control_2(phi1, phi2, cmd_s1, funky_addr_s1, data_s1, found_match_v2,
                 addr_sel_s2, ram_wen_q2, data_sel_s1, no_match_s1,
                 data_mask_io_sel_s1, port_io_sel_s1);

input phi1;
input phi2;
input [1:0] cmd_s1;
input funky_addr_s1;
input [2:0] data_s1;         // port ID

input found_match_v2;
output addr_sel_s2;
output ram_wen_q2;

output data_sel_s1;
output [2:0] no_match_s1;    // default port ID
output data_mask_io_sel_s1;  // sel for inout pads
output port_io_sel_s1;       // sel for inout pads


// output variables

reg addr_sel_s2;
reg ram_wen_q2;

reg data_sel_s1;
reg [2:0] no_match_s1;
reg data_mask_io_sel_s1; 
reg port_io_sel_s1;


// local variables

reg driving_s1;

reg [2:0] next_no_match_s2;
reg [2:0] no_match_s2;
reg [1:0] cmd_s2;
reg funky_addr_s2;
reg [2:0] data_s2;
reg driving_s2;

reg [1:0] prev_cmd_s1;
reg prev_found_match_s1;
reg prev_funky_addr_s1;
reg prev_driving_s1;


// storage between phase 1 and phase 2

always @ (phi1 or cmd_s1 or data_s1 or funky_addr_s1 or no_match_s1 or
          driving_s1)
begin
  if (phi1) begin
    `LATCH_DELAY cmd_s2           <= cmd_s1;
    `LATCH_DELAY funky_addr_s2    <= funky_addr_s1;
    `LATCH_DELAY no_match_s2      <= no_match_s1;
    `LATCH_DELAY data_s2          <= data_s1;
    `LATCH_DELAY driving_s2       <= driving_s1;
  end
end


// phase 2 control signals

always @ (phi2 or cmd_s2 or funky_addr_s2 or data_s2 or no_match_s2)
begin
  case (cmd_s2)
    `WRITE:
      begin
        addr_sel_s2 = `ADDR_SEL_CAM;
        ram_wen_q2  = 1'b1 & phi2;
        if (funky_addr_s2)
          next_no_match_s2 = data_s2[2:0];
        else
          next_no_match_s2 = no_match_s2;
      end
    `SEARCH:
      begin
        addr_sel_s2 = `ADDR_SEL_PRI;
        ram_wen_q2  = 1'b0 & phi2;
        next_no_match_s2 = no_match_s2;
      end
    `READ:
      begin
        addr_sel_s2 = `ADDR_SEL_CAM;
        ram_wen_q2  = 1'b0 & phi2;
        next_no_match_s2 = no_match_s2;
      end
    `DELETE:
      begin
        addr_sel_s2 = `ADDR_SEL_CAM;
        ram_wen_q2  = 1'b1 & phi2;   // don't-care for HW; testing requires 1
        next_no_match_s2 = no_match_s2;
      end
  endcase
end


// storage between phase 2 and phase 1

always @ (phi2 or cmd_s2 or found_match_v2 or funky_addr_s2 or driving_s2 or
          next_no_match_s2)
begin
  if (phi2) begin
    `LATCH_DELAY prev_cmd_s1         <= cmd_s2;
    `LATCH_DELAY prev_found_match_s1 <= found_match_v2;
    `LATCH_DELAY prev_funky_addr_s1  <= funky_addr_s2;
    `LATCH_DELAY prev_driving_s1     <= driving_s2;
    `LATCH_DELAY no_match_s1         <= next_no_match_s2;
  end
end

// hopefully this won't be a critical-path signal

wire reset_cmd_s1 = (funky_addr_s1 && (cmd_s1 == `DELETE)) ? 1'b1 : 1'b0;

// set io select lines based on command one state ago

always @ (prev_driving_s1 or reset_cmd_s1 or prev_cmd_s1 or
          prev_found_match_s1 or prev_funky_addr_s1)
begin
  if (prev_driving_s1 || reset_cmd_s1) begin
    data_mask_io_sel_s1 = `PAD_SEL_IN;
    port_io_sel_s1      = `PAD_SEL_IN;
    driving_s1 = 1'b0;
  end
  else begin
    case (prev_cmd_s1)
      `WRITE,
      `DELETE:
        begin
          data_sel_s1         = `DATA_SEL_RAM;  // really don't-care
          data_mask_io_sel_s1 = `PAD_SEL_IN;
          port_io_sel_s1      = `PAD_SEL_IN;
          driving_s1          = 1'b0;
        end
      `SEARCH:
        begin
          if (prev_found_match_s1)
            data_sel_s1       = `DATA_SEL_RAM;
          else
            data_sel_s1       = `DATA_SEL_NOMATCH;
          data_mask_io_sel_s1 = `PAD_SEL_IN;
          port_io_sel_s1      = `PAD_SEL_OUT;
          driving_s1          = 1'b1;
        end
      `READ:
        begin
          if (prev_funky_addr_s1)
            data_sel_s1       = `DATA_SEL_NOMATCH;
          else
            data_sel_s1       = `DATA_SEL_RAM; 
          data_mask_io_sel_s1 = `PAD_SEL_OUT;
          port_io_sel_s1      = `PAD_SEL_OUT;
          driving_s1          = 1'b1;
        end
    endcase
  end
end


endmodule // control