ram.v

一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog

`include "definitions.v"

//////////////////////////////////////////////////////////////////////////
//      Block Name      : ram.v
//      Author          : Jason Kassoff
//      Date            : 01/28/01
//      Last Revision   : 01/28/01 (by Jason Kassoff)
//
//      Block Description :
//          This block models the port-ID RAM and its surrounding circuits.
//          It is a behavioral model only (no precharging, etc.)
//
// Controls: ram_write_en_q2
// Inputs: ram_addr_v2, ram_data_s1
// Outputs: ram_data_v2
////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////
module ram(ram_write_en_q2, ram_addr_v2, ram_data_in_s1, ram_data_out_s1,
           phi1, phi2);
////////////////////////////////////////////////////////////////////////////


////////////////////////////////////////////////////////////////////////////
// Port Declarations
////////////////////////////////////////////////////////////////////////////

input ram_write_en_q2;
input [19:0] ram_addr_v2;
input [2:0] ram_data_in_s1;
output [2:0] ram_data_out_s1;
input phi1;
input phi2;

reg [2:0] ram_data_out_s1;

/////////////////////////////////////////////////////////////////////////////
// Internal Variable Declarations
/////////////////////////////////////////////////////////////////////////////

reg [4:0] ram_decode_v2;
reg [2:0] ram_storage_v2[19:0];
reg [2:0] ram_data_in_s2;
//wire [2:0] ram_read_data_v2;
reg [2:0] ram_data_out_v2;
wire [19:0] gated_addr_v2;

always @ (phi1 or ram_data_in_s1)
begin
  if (phi1) begin
    `LATCH_DELAY ram_data_in_s2 <= ram_data_in_s1;
  end
end

// Convert wordline selector to an index for the array
// of RAM storage.  This is not implemented in hardware

assign gated_addr_v2 = ram_addr_v2 & {20{phi2}};

always @ (gated_addr_v2)
begin
  case (gated_addr_v2) // really want q2 address lines
    20'h00001: ram_decode_v2 = 0;
    20'h00002: ram_decode_v2 = 1;
    20'h00004: ram_decode_v2 = 2;
    20'h00008: ram_decode_v2 = 3;
    20'h00010: ram_decode_v2 = 4;
    20'h00020: ram_decode_v2 = 5;
    20'h00040: ram_decode_v2 = 6;
    20'h00080: ram_decode_v2 = 7;
    20'h00100: ram_decode_v2 = 8;
    20'h00200: ram_decode_v2 = 9;
    20'h00400: ram_decode_v2 = 10;
    20'h00800: ram_decode_v2 = 11;
    20'h01000: ram_decode_v2 = 12;
    20'h02000: ram_decode_v2 = 13;
    20'h04000: ram_decode_v2 = 14;
    20'h08000: ram_decode_v2 = 15;
    20'h10000: ram_decode_v2 = 16;
    20'h20000: ram_decode_v2 = 17;
    20'h40000: ram_decode_v2 = 18;
    20'h80000: ram_decode_v2 = 19;
    // no wordline selected
    default: ram_decode_v2 = 20;
  endcase
end


// Write to RAM

always @(phi2 or ram_decode_v2 or ram_data_in_s2)
begin
  if (phi2) begin
    if (ram_write_en_q2 == 1'b1)
      ram_storage_v2[ram_decode_v2] = ram_data_in_s2;
  end
end


// Read from RAM

always @ (phi2 or ram_write_en_q2 or ram_decode_v2 or ram_data_in_s2)
begin
  if (ram_write_en_q2 == 1'b1)
    ram_data_out_v2 = ram_data_in_s2;
  else if (ram_decode_v2 == 20)
    ram_data_out_v2 = 3'b000;
  else begin
    if (phi2)
      ram_data_out_v2 = ram_storage_v2[ram_decode_v2];
  end
end

/*
// If no wordline was selected, pre-charged lines will result in all-1s,
//  which will be flipped in read circuit to all-0s
assign ram_read_data_v2 = (ram_decode_v2 == 20) ?
                          3'b000 : ram_storage_v2[ram_decode_v2];

// If writing, the output will be the data written in
assign ram_data_out_v2 = ram_write_en_q2 ? ram_data_in_s2 : ram_read_data_v2;
*/


// Latch output data

always @ (phi2 or ram_data_out_v2)
begin
  if (phi2)
    `LATCH_DELAY ram_data_out_s1 <= ram_data_out_v2;
end

endmodule // ram