pads.v

一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog

`include "definitions.v"

module pads(ext_phi1, ext_phi2, ext_cmd_s1, ext_addr_s1, ext_data_s1,
            ext_valid_out_s1, data_mask_io_sel_s1, port_io_sel_s1, core_phi1,
            core_phi2, cmd_s1, addr_s1, data_to_core_s1, data_from_core_s1,
            valid_out_s1);
   input         ext_phi1;
   input         ext_phi2;
   input   [1:0] ext_cmd_s1;
   input   [4:0] ext_addr_s1;
   inout  [22:0] ext_data_s1;
   output        ext_valid_out_s1;
   input         data_mask_io_sel_s1;
   input         port_io_sel_s1;
   output        core_phi1;
   output        core_phi2;
   output  [1:0] cmd_s1;
   output  [4:0] addr_s1;
   output [22:0] data_to_core_s1;
   input  [22:0] data_from_core_s1;
   input         valid_out_s1;
   
   
   // the 16 CAM data pads (all inout)
   pad pad0(ext_data_s1[0], data_to_core_s1[0], data_from_core_s1[0],
	    data_mask_io_sel_s1);
   pad pad1(ext_data_s1[1], data_to_core_s1[1], data_from_core_s1[1],
	    data_mask_io_sel_s1);
   pad pad2(ext_data_s1[2], data_to_core_s1[2], data_from_core_s1[2],
	    data_mask_io_sel_s1);
   pad pad3(ext_data_s1[3], data_to_core_s1[3], data_from_core_s1[3],
	    data_mask_io_sel_s1);
   pad pad4(ext_data_s1[4], data_to_core_s1[4], data_from_core_s1[4],
	    data_mask_io_sel_s1);
   pad pad5(ext_data_s1[5], data_to_core_s1[5], data_from_core_s1[5],
	    data_mask_io_sel_s1);
   pad pad6(ext_data_s1[6], data_to_core_s1[6], data_from_core_s1[6],
	    data_mask_io_sel_s1);
   pad pad7(ext_data_s1[7], data_to_core_s1[7], data_from_core_s1[7],
	    data_mask_io_sel_s1);
   pad pad8(ext_data_s1[8], data_to_core_s1[8], data_from_core_s1[8],
	    data_mask_io_sel_s1);
   pad pad9(ext_data_s1[9], data_to_core_s1[9], data_from_core_s1[9],
	    data_mask_io_sel_s1);
   pad pad10(ext_data_s1[10], data_to_core_s1[10], data_from_core_s1[10],
	    data_mask_io_sel_s1);
   pad pad11(ext_data_s1[11], data_to_core_s1[11], data_from_core_s1[11],
	    data_mask_io_sel_s1);
   pad pad12(ext_data_s1[12], data_to_core_s1[12], data_from_core_s1[12],
	    data_mask_io_sel_s1);
   pad pad13(ext_data_s1[13], data_to_core_s1[13], data_from_core_s1[13],
	    data_mask_io_sel_s1);
   pad pad14(ext_data_s1[14], data_to_core_s1[14], data_from_core_s1[14],
	    data_mask_io_sel_s1);
   pad pad15(ext_data_s1[15], data_to_core_s1[15], data_from_core_s1[15],
	    data_mask_io_sel_s1);
   
   // the 4 CAM mask pads (all inout)
   pad pad16(ext_data_s1[16], data_to_core_s1[16], data_from_core_s1[16],
	    data_mask_io_sel_s1);
   pad pad17(ext_data_s1[17], data_to_core_s1[17], data_from_core_s1[17],
	    data_mask_io_sel_s1);
   pad pad18(ext_data_s1[18], data_to_core_s1[18], data_from_core_s1[18],
	    data_mask_io_sel_s1);
   pad pad19(ext_data_s1[19], data_to_core_s1[19], data_from_core_s1[19],
	    data_mask_io_sel_s1);

   // the 3 RAM data pads (all inout)
   pad pad20(ext_data_s1[20], data_to_core_s1[20], data_from_core_s1[20],
	    port_io_sel_s1);
   pad pad21(ext_data_s1[21], data_to_core_s1[21], data_from_core_s1[21],
	    port_io_sel_s1);
   pad pad22(ext_data_s1[22], data_to_core_s1[22], data_from_core_s1[22],
	    port_io_sel_s1);
   
   // the valid pad (output only)
   assign ext_valid_out_s1 =  valid_out_s1;

   // the clock pads (input only)
   assign core_phi1 = ext_phi1;
   assign core_phi2 = ext_phi2;

   // the 2 command pins (input only)
   assign cmd_s1 = ext_cmd_s1;

   // the 5 addr pins (input only)
   assign addr_s1 = ext_addr_s1;
   
   
endmodule // pads   

module pad(data_world, data_to_chip, data_from_chip, io_sel);
   inout data_world;
   output data_to_chip;
   input  data_from_chip;
   input  io_sel;
   
   reg 	  data_world_temp;
   wire   data_world;
   reg 	  data_to_chip;
   
   always @ (io_sel or data_from_chip or data_world)
     begin
	if (io_sel == `PAD_SEL_OUT) begin
	   // output mode, drive inout
	   data_world_temp = data_from_chip;
	   data_to_chip = data_from_chip;
	end
	else begin
	   // input mode, read from world
	   data_to_chip = data_world;    
	   data_world_temp = 1'bz;
	end
     end
   
   assign data_world = data_world_temp;
   
endmodule // pad