chip_split.v

一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog

`include "definitions.v"

module chip(ext_phi1, ext_phi2, ext_cmd_s1, ext_addr_s1, ext_data_s1, ext_valid_out_s1);

input ext_phi1;
input ext_phi2;
input [1:0] ext_cmd_s1;
input [4:0] ext_addr_s1;
inout [22:0] ext_data_s1;
output ext_valid_out_s1;

wire core_phi1;                 // phase 1 clock driven from pads to core
wire core_phi2;                 // phase 2 clock driven from pads to core
wire [1:0] cmd_s1;              // command to controller
wire [4:0] addr_s1;             // address to controller
wire [22:0] data_to_core_s1;    // data driven from pads to core
wire [3:0] lsb_addr_q1;         // pre-decoded lsb's of addr ANDed with phi1
wire [4:0] msb_addr_s1;         // pre-decoded msb's of addr
wire cam_wen_q1;                // write (read_b) control line to CAM
wire valid_in_s1;               // valid bit from control to qualify CAM search
wire cam_reset_s1;              // reset bit tells cam when to clear valid bits
wire found_match_v2;            // indicates at least one match in prioritizer
wire addr_sel_s2;               // mux select line for RAM address mux
wire ram_wen_q2;                // write (read_b) control line to RAM
wire data_sel_s1;               // mux select line for output data mux
wire [2:0] no_match_s1;         // port ID to use if !found_match_v2 on search
wire [22:0] data_from_core_s1;  // data driven from core to pads
wire valid_out_s1;              // stored value of valid bit
wire data_mask_io_sel_s1;       // tell data and mask pads to drive or receive
wire port_io_sel_s1;            // tell port pads to drive or receive

datapath datapath(
  core_phi1,
  core_phi2,
  data_to_core_s1,
  lsb_addr_q1,
  msb_addr_s1,
  cam_wen_q1,
  valid_in_s1,
  cam_reset_s1,
  found_match_v2,
  addr_sel_s2,
  ram_wen_q2,
  data_sel_s1,
  no_match_s1,
  data_from_core_s1,
  valid_out_s1
);

wire funky_addr_s1;

control_1 control_1(
  core_phi1,
  cmd_s1,
  addr_s1,
  funky_addr_s1,
  lsb_addr_q1,
  msb_addr_s1,
  cam_wen_q1,
  valid_in_s1,
  cam_reset_s1
);

control_2 control_2(
  core_phi1,
  core_phi2,
  cmd_s1,
  funky_addr_s1,
  data_to_core_s1[`RAM_DATA],
  found_match_v2,
  addr_sel_s2,
  ram_wen_q2,
  data_sel_s1,
  no_match_s1,
  data_mask_io_sel_s1,
  port_io_sel_s1
);

pads pads(
  ext_phi1,
  ext_phi2,
  ext_cmd_s1,
  ext_addr_s1,
  ext_data_s1,
  ext_valid_out_s1,
  data_mask_io_sel_s1,
  port_io_sel_s1,
  core_phi1,
  core_phi2,
  cmd_s1,
  addr_s1,
  data_to_core_s1,
  data_from_core_s1,
  valid_out_s1
);

endmodule // chip