test.v

一个验证过的CAM源码（CAM=Content Address Memory）。语言为verilog

`define MAX_RANGE 1335:0

`define MAXCOUNT_1    1336
`define TEST_FILE_1   "./test/files/cam_test.dat"
`define OUT_FILE_1    "./test/files/cam_test.out"

`define MAXCOUNT_2    323
`define TEST_FILE_2   "./test/files/ram_test.dat"
`define OUT_FILE_2    "./test/files/ram_test.out"

`define MAXCOUNT_3    150
`define TEST_FILE_3   "./test/files/ctl_test.dat"
`define OUT_FILE_3    "./test/files/ctl_test.out"

`define MAXCOUNT_4    110
`define TEST_FILE_4   "./test/files/pri_test.dat"
`define OUT_FILE_4    "./test/files/pri_test.out"

`define CMD_RANGE   29:28
`define ADDR_RANGE  27:23
`define DATA_RANGE  22:0

module test ( phi1, phi2, command_s1, address_s1, data_s1, valid_s1);

input phi1;
input phi2;
output [1:0] command_s1;
output [4:0] address_s1;
inout [22:0] data_s1;
input valid_s1;

reg [1:0] command_s1;
reg [4:0] address_s1;
wire [22:0] data_s1;

reg [22:0] data_out_s1;

reg drive_cam_s1;
reg drive_ram_s1;
reg next_drive_cam_s1;
reg next_drive_ram_s1;

integer outfile;
integer count;
integer maxcount;
integer test_num;
reg test_done_flag;

// Tri-state logic for in-out signals

assign data_s1[`CAM_DATA] = (drive_cam_s1 == 1'b1) ?
                            data_out_s1[`CAM_DATA] : 16'bz;
assign data_s1[`CAM_MASK] = (drive_cam_s1 == 1'b1) ?
                            data_out_s1[`CAM_MASK] : 4'bz;
assign data_s1[`RAM_DATA] = (drive_ram_s1 == 1'b1) ?
                            data_out_s1[`RAM_DATA] : 3'bz;

reg [22:0] print_data;
always @ (data_s1)
begin
  print_data = data_s1;
end

// Table for storing stimuli
reg [29:0] test_table[`MAX_RANGE];
reg [29:0] stimulus;


initial
  begin
    $display("Begin testing...");

    // initially hi-z data lines just in case chip wakes up driving them out

    drive_cam_s1 = 1'b0;
    drive_ram_s1 = 1'b0;
    next_drive_cam_s1 = 1'b0;
    next_drive_ram_s1 = 1'b0;
    
    // make sure nothing runs until test is initialized

    count = 0;
    maxcount = 0;
    test_num = 1;
    test_done_flag <= 1;

  end

always @ (posedge phi2)
  begin

    // Run test file 1

    if (test_num == 1 && test_done_flag == 1) begin
      $display(`TEST_FILE_1);
      outfile = $fopen(`OUT_FILE_1);
      count = 0;
      maxcount = `MAXCOUNT_1;
      $readmemb(`TEST_FILE_1, test_table);  
      test_done_flag = 0;
    end

    // Run test file 2

    if (test_num == 2 && test_done_flag == 1) begin
      $display(`TEST_FILE_2);
      outfile = $fopen(`OUT_FILE_2);
      count = 0;
      maxcount = `MAXCOUNT_2;
      $readmemb(`TEST_FILE_2, test_table);  
      test_done_flag = 0;
    end

    // Run test file 3

    if (test_num == 3 && test_done_flag == 1) begin
      $display(`TEST_FILE_3);
      outfile = $fopen(`OUT_FILE_3);
      count = 0;
      maxcount = `MAXCOUNT_3;
      $readmemb(`TEST_FILE_3, test_table);  
      test_done_flag = 0;
    end

    // Run test file 4

    if (test_num == 4 && test_done_flag == 1) begin
      $display(`TEST_FILE_4);
      outfile = $fopen(`OUT_FILE_4);
      count = 0;
      maxcount = `MAXCOUNT_4;
      $readmemb(`TEST_FILE_4, test_table);  
      test_done_flag = 0;
    end

    // Finished

    if (test_num == 5) $finish;

  end


always @ (posedge phi2)
begin
  data_out_s1 = 23'h66beef;
  drive_cam_s1 = next_drive_cam_s1;
  drive_ram_s1 = next_drive_ram_s1;

  if (drive_cam_s1 && drive_ram_s1) begin

    if (count < maxcount) begin
      stimulus = test_table[count];
      command_s1  = stimulus[`CMD_RANGE];
      address_s1  = stimulus[`ADDR_RANGE];
      data_out_s1 = stimulus[`DATA_RANGE];
      // set next_drive_cam_s1 and next_drive_ram_s1
      // based on current command
      case (command_s1)
        `WRITE:
          begin
            next_drive_cam_s1 = 1'b1;
            next_drive_ram_s1 = 1'b1;
          end
        `SEARCH:
          begin
            next_drive_cam_s1 = 1'b1;
            next_drive_ram_s1 = 1'b0;
          end
        `READ:
          begin
            next_drive_cam_s1 = 1'b0;
            next_drive_ram_s1 = 1'b0;
          end
        `DELETE:
          begin
            next_drive_cam_s1 = 1'b1;
            next_drive_ram_s1 = 1'b1;
          end
      endcase
      count = count + 1;
    end
    else if (test_done_flag == 0) begin
      // do a reset
      command_s1 = `DELETE;
      address_s1 = `FUNKY_ADDR;
      // then start the next test
      test_num = test_num + 1;
      test_done_flag = 1;
    end
  end

  else begin
    // if either drive_cam_s1 or drive_ram_s1 was not
    // set this time, set it next time, because the
    // read or search has completed
    next_drive_cam_s1 = 1'b1;
    next_drive_ram_s1 = 1'b1;
  end

end

always @ (posedge phi1)
begin
  if (!drive_cam_s1 || !drive_ram_s1) begin
    // we must be getting some output from the chip,
    // so write it out to a file
    if (command_s1 == `SEARCH) begin
      $fdisplay(outfile, "SRCH : %x", data_s1[`RAM_DATA]);
    end
    else if (command_s1 == `READ) begin
      if (address_s1 == 5'b11111) begin
        $fdisplay(outfile, "RDID : %x", data_s1[`RAM_DATA]);
      end
      else begin
      $fdisplay(outfile, "READ : %x %x %x %x",
                data_s1[`RAM_DATA], data_s1[`CAM_MASK], data_s1[`CAM_DATA],
                valid_s1);
      end
    end
    else begin
      // might happen before reset when x's are around
    end
  end
end


always @ (command_s1 or drive_cam_s1)
begin
  if (drive_cam_s1 && drive_ram_s1) begin
    case (command_s1)
      `WRITE:
        begin
          next_drive_cam_s1 = 1'b1;
          next_drive_ram_s1 = 1'b1;
        end
      `SEARCH:
        begin
          next_drive_cam_s1 = 1'b1;
          next_drive_ram_s1 = 1'b0;
        end
      `READ:
        begin
          next_drive_cam_s1 = 1'b0;
          next_drive_ram_s1 = 1'b0;
        end
      `DELETE:
        begin
          next_drive_cam_s1 = 1'b1;
          next_drive_ram_s1 = 1'b1;
        end
    endcase
  end
  else begin
    next_drive_cam_s1 = 1'b1;
    next_drive_ram_s1 = 1'b1;
  end
end

endmodule